CS42428 datasheet(14/67 Pages) CIRRUS

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CS42428

3.4

Clock Generation

The clock generation for the CS42428 is shown in the figure below. The internal MCLK is derived from

the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the

SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of

PLL lock to the other source input.

3.4.1

PLL and Jitter Attenuation

The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and

generate the required internal master clock frequency. There are some applications where low jitter in the

recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to

have good jitter attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock

Control (address 06h)” on page 37, the PLL will lock to the incoming ADC_LRCK and generate an output

master clock (RMCK) of 256Fs. Table 3 below shows the output of the PLL with typical input Fs values

for ADC_LRCK.

The PLL behavior is affected by the external filter component values. Figure 1 shows the required config-

uration of the external filter components. The set of component values required for 32 kHz to 192 kHz

ADC_LRCK

(slave mode)

PLL (256Fs)

8.192 -

49.152 MHz

P LL_LRCK bit

SW_CTRLx bits

(manual or auto

switch)

OMCK

Auto Detect

Input Clock

1,1.5, 2, 4

single

speed

256

double

speed

128

quad

speed

single

speed

double

speed

quad

speed

not O LM

OLM #1

DAC _FMx bits

ADC_ FMx bits

DAC_OLx

ADC_O Lx bits

ADC_O Lx and

ADC _S P SELx b its

ADC_SCLK

DAC_SCLK

D AC_LRCK

ADC_LRCK

RMCK

OLM #2

not O LM

OLM #1

OLM #2

128FS

256FS

128FS

256FS

Internal

MCLK

RMCK_DIVx bits

Figure 6. Clock Generation

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