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TDA4VM Datasheet(PDF) 4 Page - Texas Instruments |
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TDA4VM Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 311 page  C7x DSP w/ MMA Navigator Subsystem Memory Subsystem 8MB SRAM with ECC MSMC System Services Spinlock GP Timers Mailboxes Capture Subsystem CSI2 4L TX 2 CSI2 4L RX × Navigator Subsystem Channelized FW MCRC RA INTR UDMA INTA Proxy DMSC Safety DTK SP RAM 512B 10 GP Timers × 2 WWDT × SA2UL MCU Island Interconnect Control Interfaces Media and Data Storage General Connectivity High-Speed Serial Interfaces eMMC Audio Peripherals 12 MCASP × 3 eQEP × 3 eCAP × 6 eHRPWM × 2 I2C × 7 I2C × 2 GPIO × 8 MCSPI × 3 MCSPI × 2 ADC × 10 UART × (1) UART (1) (1) (1) 10/100/1000 Ethernet (1) TDA4VM 4 PCIe 2-Lane Ports × (2) ® intro_001 (with optional Lockstep) 2 Arm × ® Cortex -R5F ® 64K L2 RAM per Core 512KB L2 with ECC 1MB Shared L2 Cache with ECC Dual Arm® Cortex -A72 ® 4 Arm × ® Cortex -R5F ® GPMC EMIF 32 LPDDR4 w/ECC -bit ELM 512KB SRAM Display Subsystem 4K Blend Scale Convert DSI DP/eDP (2) UDMA WWDT SMMU 1 MB SRAM Channelized FW CPTS Mailbox TIMER_MGR PVU INTR SecProxy MCRC INTA UDMA Proxy/RA Spinlock SMMU PAT Ethernet Subsystem (Supporting up to 4 external ports) Integrated Ethernet Switch (2) Security Accelerators AES SHA RNG DES PKA 3DES Video Acceleration (H.264 Encode and H.264/H.265 Decode) VPAC DMPAC 2× C66x DSP 3D GPU PowerVR Rogue 8XE GE8430 2 SD/SDIO × UFS 2L 1 OSPI or 1 HyperBus × × (1)(3) (1)(3) 1 QSPI × 2 I3C × (1) I3C 2 USB 3.0 DRD × (2) Automotive Interfaces 2 CAN-FD × (1) 14 CAN-FD × Ethernet Switch (Up to 8-ports) QSGMII/SGMII/RGMII/RMII (2) Debug 4 TDA4VM SPRSP36E – FEBRUARY 2019 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: TDA4VM Device Overview Copyright © 2019, Texas Instruments Incorporated 1.4 Functional Block Diagram Figure 1-1 is functional block diagram for the device. (1) This interface is located on the MCU Island but is available for the full system to access. (2) DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes. (3) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus™ and OSPI1. Figure 1-1. Functional Block Diagram |
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