ST92195D datasheet(61/249 Pages) STMICROELECTRONICS

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ST92195C/D - RESET AND CLOCK CONTROL UNIT (RCCU)

Table 10. Oscillator Transconductance

Figure 29. Crystal Oscillator

Note: Depending on the application it may be better not to

implement CL1.

Figure 30. Internal Oscillator Schematic

Figure 31. External Clock

The following table is relative to the fundamental

quartz crystal only; assuming:

– Rs: parasitic series resistance of the quartz crys-

tal (upper limit)

– C0: parasitic capacitance of the crystal (upper

limit,

≤ 7 pF)

– C1,C2: maximum total capacitance on pins OS-

CIN/OSCOUT (value including external capaci-

tance tied to the pin plus the parasitic

capacitance of the board and device).

Table 11. Crystal Specification (C0

≤ 7pF)

Legend:

Rs: Parasitic Series Resistance of the quartz crystal (up-

per limit) C0: Parasitic capacitance of the quartz crystal

(upper limit, < 7pF)

CL1, CL2: Maximum Total Capacitance on pins OSCIN

and OSCOUT (the value includes the external capaci-

tance tied to the pin plus the parasitic capacitance of the

board and of the device)

gm: Transconductance of the oscillator

Note.The tables are relative to the fundamental quartz

crystal only (not ceramic resonator).

Min

Typ

Max

mA/V

0.77

1.5

2.4

OSCIN

OSCOUT

CL1

CL2

ST9

CRYSTAL CLOCK

HALT

OSCIN

OSCOUT

RIN

ROUT

OSCIN

OSCOUT

CLOCK

INPUT

EXTERNAL CLOCK

Freq.

MHz.

CL1 = CL2 = 39 pF

Rs Max

865

260

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