ST92195D datasheet(118/249 Pages) STMICROELECTRONICS

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ST92195C/D - ON SCREEN DISPLAY (OSD)

ON SCREEN DISPLAY (Cont’d)

7.4.6.4 Building a Parallel Mode, 40 Char, Line

mode Display

Half-Page Location

The pair of adjacent 0.5 Kbyte blocks of half page

content is stored in the TDSRAM location pointed

to by the PG3..PG0 bits. One block contains the

characters, the other block contains the attribute

bytes.

Header & Status Rows Location

The 0.5 Kbyte block containing the Header, Status

Row 0 and Status Row 1 is pointed to by the

HS3..HS0 bits.

The Header/Status attributes are stored in this

block at offset 80h.

The Row attribute (row count) is stored in this

block at offset 100h and contains 12 bytes for line

mode (see DCM1R register description).

Row Scrolling Buffer Location

The scrolling buffer corresponds to the Row 12

when the scrolling feature is used (in this case 11

rows are scrolled).

Figure 74. Parallel (40 Characters) Line Mode Mapping

See Figure 70 on page 115 for Ad-

Resolution 1K bytes

See Figure 69 on page 115 for Ad-

0.5K TDSRAM

Header Char.

Resolution 0.5K bytes

Status Row 0

Status Row 1

Free Space

Header Attr.

Status Row 0

Status Row 1

Free Space

Row Attr.

80h

100h

0.5K TDSRAM

Row 1 Attr.

Row 11 Attr.

Free Space

Row 12/Scrolling Buffer

Row 1 Char.

Row 11 Char.

Free Space

Row 12/Scrolling Buffer

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