AX58200BT datasheet(101/180 Pages) ASIX

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101

AX58200

EtherCAT Slave Controller SoC

ESC (EtherCAT) Sub-system

2.43.1 Overview

The AX58200 implements a 2/3-port EtherCAT slave controller (ESC), licensed from Beckhoff Automation, with

9 Kbytes Process Data RAM, 8 Fieldbus Memory Management Units (FMMUs), 8 Sync-Managers and a 64-bit

Distributed Clock.

Port 0 and 1 integrate embedded Ethernet PHYs, and port 2 is an optional MII interface which are multi-function

pins shared with other interfaces (i.e. PWM, Hall, etc.). Packets are forwarded in the following order: Port 0-

>EtherCAT Processing Unit->Port 1->Port 2.

The AX58200 supports function register mirror from/to ESC memory space. The mirror registers located at process

data memory address from 0x3000 to 0x33FF.

For detailed information about the EtherCAT technology, the EtherCAT core mechanisms, and major features, we

refer to the official standard documentations and guidelines available from ETG (www.ethercat.org, ETG.1000),

IEC (http://www.iec.ch, IEC61158, IEC61784-2, IEC 61800-7), and Beckhoff (http://www.beckhoff.de, technical

specification) web sites.

The AX58200 requires a crystal (25MHz, ±25 PPM at room temperature) as the clock source. Internal PLL

generates the 100MHz clock for EtherCAT Slave Controller (ESC) and also for other functions.

The AX58200 has three reset sources. First, during the VCCK power-on, the internal Power-On-Reset (POR) can

generate a reset pulse to reset all the function blocks when the VCCK power pin rises to a certain threshold voltage

level. The second reset is RSTn pin, which is to do the fundamental reset. And third, EtherCAT command reset,

the EtherCAT master can send reset sequence to force AX58200 reset. AX58200 also supports a reset output

RSTO polarity bootstrap configuration (RSTO_POL).

AX58200BT Datasheet(PDF) 101 Page - ASIX Electronics Corporation