AX58200BT datasheet(51/180 Pages) ASIX

51 / 180 page

AX58200

EtherCAT Slave Controller SoC

EMC

HSUSBH

USBH

Crypto

SDIO0

M4-SBUS

M4-IBUS

M4-DBUS

FLASH

SRAM1

(32K)

SRAM2

(96K)

APB1

APB2

EBI

AHB

(ctrl)

PDMA

SPIM

SPIM DMA

HSUSBD

SDIO1

SRAM3

(32K)

Figure 2.2-11: Bus Matrix Diagram

2.2.9

HIRC Auto Trim

This chip supports auto-trim function: the HIRC trim (48 MHz RC oscillator), according to the accurate external

32.768 KHz crystal oscillator or internal USB synchronous mode, automatically gets accurate HIRC output

frequency, 0.25 % deviation within all temperature ranges.

For instance, the system needs an accurate 12 MHz clock. In such case, if neither using use PLL as the system

clock source nor soldering 32.768 KHz crystal in system, user has to set REFCKSEL (SYS_IRCTCTL[10]

reference clock selection) to “1”, set FREQSEL (SYS_IRCTCTL[1:0] trim frequency selection) to “01”, and the

auto-trim function will be enabled. Interrupt status bit FREQLOCK (SYS_IRCTISTS[8] HIRC frequency lock

status) “1” indicates the HIRC output frequency is accurate within 0.25% deviation.

2.2.10 Register Lock Control

Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip

operation. These system control registers are protected after the power-on reset till user to disable register

protection. For user to program these protected registers, a register protection disable sequence needs to be

followed by a special programming. The register protection disable sequence is writing the data “59h”, “16h”

“88h” to the register SYS_REGLCTL address at 0x4000_0100 continuously. Any different data value, different

sequence or any other write to other address during these three data writing will abort the whole sequence.

SYS_IPRST0

Address 0x4000_0008

SYS_ALTCTL

address 0x4000_0014

SYS_BODCTL

address 0x4000_0018

SYS_PORCTL

address 0x4000_0024

SYS_VREFCTL

address 0x4000_0028

AX58200BT Datasheet(PDF) 51 Page - ASIX Electronics Corporation

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