1

®

FN8172.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

X9268

Dual Supply/Low Power/256-Tap/2-Wire Bus

Dual Digitally-Controlled (XDCP™)

Potentiometers

FEATURES

• Dual–Two separate potentiometers

• 256 resistor taps/pot–0.4% resolution

• 2-Wire Serial Interface for write, read, and

transfer operations of the potentiometer

• Wiper Resistance, 100

Ω typical @ V+ = 5V,

V- = -5V

• 16 Nonvolatile Data Registers for Each

Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position

on Power-up.

• Standby Current < 5µA Max

•50k

Ω, 100kΩ versions of End to End Pot

Resistance

• Endurance: 100,000 Data Changes per Bit per

Register

• 100 yr. Data Retention

• 24-Lead SOIC, 24-Lead TSSOP

• Low Power CMOS

V+ = 2.7V to 5.5V

V- = -2.7V to -5.5V

DESCRIPTION

The

X9268

integrates

2

digitally

controlled

potentiometer

(XDCP)

on

a

monolithic

CMOS

integrated circuit.

The digital controlled potentiometer is implemented

using 255 resistive elements in a series array.

Between each element are tap points connected to the

wiper terminal through switches. The position of the

wiper on the array is controlled by the user through the

2-Wire

bus

interface.

Each

potentiometer

has

associated with it a volatile Wiper Counter Register

(WCR) and a four nonvolatile Data Registers that can

be directly written to and read by the user. The

contents of the WCR controls the position of the wiper

on the resistor array though the switches. Powerup

recalls the contents of the default Data Register (DR0)

to the WCR.

The

XDCP

can

be

used

as

a

three-terminal

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

FUNCTIONAL DIAGRAM

2-Wire

Bus

50k

Ω or 100kΩ versions

Power-on Recall

Wiper Counter

Registers (WCR)

Data Registers

(DR0–DR3)

Interface

Bus

Interface

and Control

Address

Data

Status

Write

Read

Transfer

Inc/Dec

Control

V-

Data Sheet

June 21, 2005