A6821 datasheet(3/9 Pages) ALLEGRO

3 / 9 page

Worcester, Massachusetts 01615-0036 (508) 853-5000

115 Northeast Cutoff, Box 15036

www.allegromicro.com

A6821

DABiC-5 8-Bit Serial Input Latched Sink Drivers

ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd= 3.0 V to 5.5 V

Characteristic

Symbol

Test Conditions

Vdd = 3.3 V

Vdd = 5 V

Units

Min.

Typ.

Max. Min.

Typ.

Max.

Output Leakage Current

ICEX

VOUT = 50 V

–

μA

Collector–Emitter Saturation

Voltage

VCE(SAT)

IOUT = 100 mA

–

1.1

–

1.1

IOUT = 200 mA

–

1.3

–

1.3

IOUT = 350 mA

–

1.6

–

1.6

Input Voltage

VIN(1)

2.2

–

3.3

–

VIN(0)

–

1.1

–

1.7

Input Resistance

RIN

–

kΩ

Serial Data Output Voltage

VOUT(1)

IOUT = –200 μA

2.8

3.05

–

4.5

4.75

–

VOUT(0)

IOUT = 200 μA

–

0.15

0.3

–

0.15

0.3

Maximum Clock Frequency2

–

MHz

Logic Supply Current

IDD(1)

One output on, OE = L, ST = H

–

2.0

–

2.0

IDD(0)

All outputs off, OE = H, ST = H,

P1 through P8 = L

–

100

–

100

μA

Output Enable-to-Output Delay

tdis(BQ)

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

ten(BQ)

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Strobe-to-Output Delay

tp(STH-QL) VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

tp(STH-QH) VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Output Fall Time

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Output Rise Time

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Clock-to-Serial Data Out Delay

tp(CH-SQX) IOUT = ±200 μA

–

1Positive (negative) current is deﬁned as conventional current going into (coming out of) the speciﬁed device pin.

2Operation at a clock frequency greater than the speciﬁed minimum value is possible but not warranteed.

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

OE = Output Enable

ST = Strobe

Serial

Shift Register Contents Serial

Latch Contents

Output

Output Contents

Data Clock

Data

Strobe

Enable

Input

I1 I2 I3 ... I8

Output

Input

I1 I2 I3 ... I8

Input

I1 I2 I3 ... I8

R2 R3 ... R8

XXX... X

R1 R2 ... R7

R1 R2 R3 ... R8

P1 P2 P3 ... P8

P1 P2 P3 ... P81 P2 P3 ... P8

XXX... X

R1 R2 ... R7

...

Truth Table

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