SA630

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 3 — 23 July 2014

9 of 20

NXP Semiconductors

SA630

Single-Pole Double-Throw (SPDT) switch

14. Application information

The typical application schematic and printed-circuit board layout of the SA630 evaluation

board is shown in Figure 19. The layout of the board is simple, but a few cautions must be

observed. The input and output traces should be 50

. If a symmetric isolation between

the two channels is desired, then the placement of the AC bypass capacitor is extremely

critical. The trace from AC_GND (pin 7) should be drawn back towards the package and

then be routed downwards. The capacitor should be placed straight down as close to the

device as practical.

For better isolation between the two channels at higher frequencies, it is also advisable to

run the two output/input traces at an angle. This arrangement also minimizes any

inductive coupling between the two traces. The power supply bypass capacitor should be

placed close to the device. Figure 5 shows the frequency response of the SA630. The

loss matching between the two channels is excellent to 1.2 GHz, as shown in Figure 7.

a. Evaluation board schematic

b. SA630 board layout

Fig 19. Evaluation board and layout

aaa-013989

OUT1

0.01 μF

SA630

1

2

3

4

6

5

8

7

AC_GND

0.01 μF

GND

OUT2

0.01 μF

+5 V

0.1 μF

GND

0.01 μF

INPUT

ENCH1

aaa-013990