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SL2S5002FUD Datasheet(PDF) 8 Page - NXP Semiconductors |
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SL2S5002FUD Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 35 page  SL2S5002_SL2S5102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.4 — 27 August 2012 193134 8 of 35 NXP Semiconductors SL2S5002; SL2S5102 ICODE SLIX-L 8.1.1 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 6 “General specification for 8” wafer on UV-tape with electronic fail die marking”. 8.1.2 Map file distribution See Ref. 6 “General specification for 8” wafer on UV-tape with electronic fail die marking”. Height uniformity within a die 2 m within a wafer 3 m wafer to wafer 4 m Bump flatness 1.5 m Bump size LA, LB 60 m 60 m TEST, GND 60 m 60 m variation 5 m Under bump metallization sputtered TiW Table 4. Wafer specification |
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