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DF2B5M4ASL Datasheet(PDF) 2 Page - Toshiba Semiconductor |
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DF2B5M4ASL Datasheet(HTML) 2 Page - Toshiba Semiconductor |
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2 / 9 page ![]() DF2B5M4ASL 2 5. 5. 5. 5. Example of Circuit Diagram Example of Circuit Diagram Example of Circuit Diagram Example of Circuit Diagram 6. 6. 6. 6. Quick Reference Data Quick Reference Data Quick Reference Data Quick Reference Data Characteristics Working peak reverse voltage Total capacitance Dynamic resistance Electrostatic discharge voltage (IEC61000-4-2) (Contact) Symbol VRWM Ct RDYN VESD Note (Note 1) (Note 2) (Note 3) Test Condition VR = 0 V, f = 1 MHz Min Typ. 0.15 0.7 Max 3.6 0.2 16 Unit V pF Ω kV Note 1: Recommended operating condition. Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A. Note 3: Criterion: No damage to devices. 2019-08-05 Rev.1.0 ©2019 Toshiba Electronic Devices & Storage Corporation |
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