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FXPS7400DI4 Datasheet(PDF) 41 Page - NXP Semiconductors

Part # FXPS7400DI4
Description  Digital absolute pressure sensor, 20 to 400 kPa
PDF  71 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXPS7400DI4 Datasheet(HTML) 41 Page - NXP Semiconductors

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NXP Semiconductors
FXPS7400D4
Digital absolute pressure sensor, 20 to 400 kPa
FXPS7400D4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 5 — 15 July 2019
41 / 71
Table 60. I2C_ADDRESS - I2C slave address register (address 3Fh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
I2C_ADDRESS[7:0]
Factory Default (stored value)
0
0
0
0
0
0
0
0
Factory Default (read value)
0
1
1
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The default register value is 00h. If the register value is 00h, the I2C slave address is
60h and a value of 60h is transmitted in response to a read command. If the register is
written to a value other than 00h, the I2C slave address is the lower seven bits of the
actual register value and the actual register value is transmitted in response to a read
command.
7.7.12 DSP Configuration Registers (DSP_CFG_Ux)
The DSP Configuration registers (DSP_CFG_Ux) are a series of registers that affect the
DSP data path.
There are 5 DSP Configuration registers, however, only DSP_CFG_U1, DSP_CFG_U4
and DSP_CFG_U5 are used when the device is in SPI or I2C mode. The DSP_CFG_U2
and DSP_CFG_U3 registers are for factory use only and are used for internal tests.
7.7.12.1 DSP_CFG_U1 - DSP user configuration #1 register (address 40h)
The DSP user configuration register #1 is a user programmable read/write register that
contains DSP specific configuration information. This register is included in the read/write
array error detection.
Changes to this register reset the DSP data path. The contents of the SNSDATA_x
registers are not guaranteed until the DSP has completed initialization as specified in
Table 101. Reads of the SNSDATA_x registers and sensor data requests should be
prevented during this time.
Table 61. DSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
LPF[3:0]
reserved
reserved
USER_RANGE[1]
USER_RANGE[0]
Factory default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 62. Low-pass filter selection bits (LPF[3:0])
LPF[3]
LPF[2]
LPF[1]
LPF[0]
Low Pass Filter Type
0
0
0
0
370 Hz, 2-Pole
0
0
0
1
400 Hz, 3 Pole
0
0
1
0
800 Hz, 4-Pole
0
1
0
0
1000 Hz, 4-Pole
0
1
0
1
reserved
0
1
1
0
reserved
0
1
1
1
reserved
1
0
0
0
reserved
1
x
x
x
reserved



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