SSD1818 Series
Rev 1.2
08/2002
SOLOMON
9
M/ S
This pin is the master/slave mode selection input. When this pin is pulled high, master mode is selected.
CL, M, MSTAT and DOF signals will be the output pins for slave devices.
When this pin is pulled low, slave mode is selected. CL, M, DOF are input pins getting signal from master
device. The state of MSTAT will be high impedance.
CLS
This pin is the internal clock enable pin. When this pin is pulled high, internal clock is enabled.
The internal clock will be disabled when CLS is pulled low. Under such circumstances, an external clock
source must be fed into the CL pin.
C68/ 80
This pin is the MCU parallel interface selection input. When the pin is pulled high, 6800 series interface is
selected. When the pin is pulled low, 8080 series interface is selected.
If Serial Interface is selected (P/ S pulled low), the setting of this pin is ignored. The C68/ 80 pin must be
connected to a known logic state (either high or low).
P/ S
This pin is the serial/parallel interface selection input. When this pin is pulled high, parallel interface mode
is selected. When this pin is pulled low, serial interface will be selected.
Note1: For serial mode, D0, D1, D2, D3, D4, D5, R/ W ( WR ), E/(
RD ) are recommended to connect to
Vss.
Note2: Read back operation is only available in parallel mode.
C1, C0
These two pins should connect to VDD operation.
IRS
This is the input pin to enable the internal resistors network for the voltage regulator. This pin should be
connected to VDD for any circumstances.
SPI
This is the input pin to enable the circuitry for providing serial interface. This pin must be connected to low
at any circumstances. When the SPI pin and the P/ S , selection input are both pulled low, the serial
interface is enabled. When the SPI pin is pulled low and the P/ S selection input is pulled high, the
parallel interface is enabled.
NC/TEST0 – TEST2/T0 – T3
These are the No Connection pins. These pins should be left open individually.
Remarks: These pins should not be connected together.
ROW0 - ROW63
These pins provide the Common driving signals to the LCD panel. Please refer to the Table 3 on Page 11
for the COM signal mapping.
SEG0 - SEG103
These pins provide the LCD segment driving signals. The output voltage level of these pins is VDD during
sleep mode or standby mode.
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