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M58LT128GST Datasheet(PDF) 22 Page - STMicroelectronics |
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M58LT128GST Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 98 page ![]() 4 Command Interface M58LT128GST, M58LT128GSB 22/98 See Appendix C, Figure 19: Program Flowchart and Pseudo Code, for the flowchart for using the Program command. 4.8 Buffer Program command The Buffer Program Command makes use of the device’s 32-Word Write Buffer to speed up programming. Up to 32 Words can be loaded into the Write Buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard non- buffered Program command. Four successive steps are required to issue the Buffer Program command. 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, read operations in the bank will output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of Words to be programmed. Value n is written to the same block address, where n+1 is the number of Words to be programmed. 3. Use n+1 Bus Write cycles to load the address and data for each Word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n. Optimum performance is obtained when the start address corresponds to a 32 Word boundary. If the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program Command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. During Buffer Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 20: Buffer Program Flowchart and Pseudo Code, for a suggested flowchart on using the Buffer Program command. |
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