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M58LT128GSB Datasheet(PDF) 21 Page - STMicroelectronics

Part # M58LT128GSB
Description  128Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Secure Flash Memories
PDF  98 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M58LT128GSB Datasheet(HTML) 21 Page - STMicroelectronics

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M58LT128GST, M58LT128GSB
4 Command Interface
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4.6
Block Erase command
The Block Erase command is used to erase a block. It sets all the bits within the selected block
to ’1’. All previous data in the block is lost.
If the block is protected then the erase operation will abort, the data in the block will not be
changed and the Status Register will output the error.
Two Bus Write cycles are required to issue the command.
1.
The first bus cycle sets up the Block Erase command.
2.
The second latches the block address and starts the Program/Erase Controller.
If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5
are set and the command is aborted.
Once the command is issued the bank enters Read Status Register mode and any read
operation within the addressed bank will output the contents of the Status Register. A Read
Array command is required to return the bank to Read Array mode.
During Block Erase operations the bank containing the block being erased will only accept the
Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored.
The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be
guaranteed when the Block Erase operation is aborted, the block must be erased again.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being erased.
Typical Erase times are given in Table 16: Program/Erase Times and Endurance Cycles.
See Appendix C, Figure 22: Block Erase Flowchart and Pseudo Code, for a suggested
flowchart for using the Block Erase command.
4.7
Program command
The program command is used to program a single Word to the memory array.
Two Bus Write cycles are required to issue the Program Command.
1.
The first bus cycle sets up the Program command.
2.
The second latches the address and data to be programmed and starts the Program/
Erase Controller.
Once the programming has started, read operations in the bank being programmed output the
Status Register content.
During a Program operation, the bank containing the Word being programmed will only accept
the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the
Program/Erase Suspend command, all other commands will be ignored. A Read Array
command is required to return the bank to Read Array mode.
Refer to Dual Operations section for detailed information about simultaneous operations
allowed in banks not being programmed.
Typical Program times are given in Table 16: Program/Erase Times and Endurance Cycles.
The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed
when the Program operation is aborted, the Word must be reprogrammed.



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