RA4W1 datasheet(54/105 Pages) RENESAS

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R01DS0359EJ0100 Rev.1.00

Page 54 of 105

Mar 31, 2020

RA4W1 Datasheet

2. Electrical Characteristics

2.3.6

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing

Note 1.

Constraints on input cycle:

When not switching the source clock: tPcyc × 2 < tACYC should be satisfied.

When switching the source clock: tPcyc × 6 < tACYC should be satisfied.

Note:

tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle

Figure 2.36

I/O ports input timing

Figure 2.37

POEG input trigger timing

Figure 2.38

GPT input capture timing

Table 2.32

I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing

Parameter

Symbol Min

Max

Unit

Test

conditions

I/O ports

Input data pulse width

tPRW

1.5

tPcyc

Figure 2.36

Input/output data cycle (P004)

tPOcyc

POEG

POEG input trigger pulse width

tPOEW

tPcyc

Figure 2.37

GPT

Input capture pulse width

Single edge

tGTICW

1.5

tPDcyc

Figure 2.38

Dual edge

2.5

AGT

AGTIO, AGTEE input cycle

2.7 V ≤ VCC ≤ 3.6 V

tACYC*1 250

Figure 2.39

2.4 V ≤ VCC < 2.7 V

500

1.8 V ≤ VCC < 2.4 V

1000

AGTIO, AGTEE input high level

width, low-level width

2.7 V ≤ VCC ≤ 3.6 V

tACKWH,

tACKWL

100

2.4 V ≤ VCC < 2.7 V

200

1.8 V ≤ VCC < 2.4 V

400

AGTIO, AGTO, AGTOB output

cycle

2.7 V ≤ VCC ≤ 3.6 V

tACYC2

62.5

Figure 2.39

2.4 V ≤ VCC < 2.7 V

125

1.8 V ≤ VCC < 2.4 V

250

ADC14

14-bit A/D converter trigger input pulse width

tTRGW

1.5

tPcyc

Figure 2.40

KINT

KRn (n = 00 to 07) pulse width

tKR

250

Figure 2.41

Port

tPRW

POEG input trigger

tPOEW

Input capture

tGTICW

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