88

SYMBOL/PARAMETER

MIN .

TYP.

MAX.

UNITS

t

W

R/C Pulse Width

40

ns

t

DBC

BUSY delay from R/C

80

150

ns

t

B

BUSY LOW

2.47

2.7

µs

t

AP

Aperture Delay

13

ns

∆t

AP

Aperture Jitter

150

ps, rms

t

C

Conversion Time

2.5

2.70

µs

t

DBE

BUSY from End of Conversion

100

ns

t

DB

BUSY Delay after Data Valid

25

75

200

ns

t

A

Acquisition Time

130

300

ns

t

Throughput Time

SP8603

3.0

µs

SP8605

5.0

µs

SP8610

10.0

µs

t

HDR

Valid Data Held After R/C LOW

20

50

ns

t

S

CS or HBE LOW before R/C Falls

25

5

ns

t

H

CS or HBE LOW after R/C Falls

25

0

ns

t

DD

Data Valid from CS LOW, R/C HIGH, and HBE

65

150

ns

in Desired State (Load = 100pF)

t

HL

Delay to Hi-Z State after R/C Falls or

50

150

ns

CS Rises (3K

Ω Pullup or Pulldown

All parameters Guaranteed By Design.

AC DYNAMIC TIMING DATA

layout of the circuit in front of the SP86XX Series.

Finally, in multiplexed systems, the timing relative to

when the multiplexer is switched may affect the

analog performance of the system. In most applica-

tions, the multiplexer can be switched as soon as R/C

goes LOW (with appropriate delays), but this may

affect the conversion if the switched signal shows

glitches or significant ringing at the SP86XX Series

input. Whenever possible, it is safer to wait until the

conversion is completed before switching and multi-

plexer. The extremely fast acquisition time and con-

version time of the SP86XX Series make this practi-

cal in many applications.

R/C, it makes sense to keep the rising edge of the

convert pulse outside the time when bit decisions are

being made. In other words, the convert pulse should

eitherbeshort(under100nssothatittransitionsbefore

the MSB decision), or relatively long (i.e., for the

SP8603, over 2.75

µs to transition after the LSB

decision).

Next, although the data outputs are forced into a Hi-Z

state during conversion, fast bus transients can still be

capacitively coupled into the SP86XX Series. If the

data bus experiences fast transients during conver-

sion, these transients can be attenuated by adding a

logicbuffertothedataoutputs.TheBUSYoutputcan

be used to enable the buffer.

Naturally, transients on the analog input signal are to

be avoided, especially at times within

±20ns of R/C

going LOW, when they may be trapped as part of the

charge on the capacitor array. This requires careful