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28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update

Errata

5.

28F160C3xC and 28F640C3xC Lock/Unlock/Lock-Down Operation

Problem:

On the 16Mb and 64Mb 0.18µm devices, if CE# is deasserted after any block lock operation and

before the next write sequence, the part may perform the same operation on additional blocks. (See

waveform below.)

Implication:

When CE#is deasserted afterperforminga blocklockoperationto a specific blockand priortothe

next write sequence, other blocks may perform the same operation.

Workaround:

Depending on software implementation, systems may already be effectively managing this

erratum. There is currently a workaround for this erratum:

Immediately after performing a block lock, unlock, or lock-down operation, perform a valid write

sequence before chip enable (CE#) is deasserted.

For example, one possible solution is shown below:

1) Assert CE# and toggle WE# to write the block lock setup command (0x60).

2) Toggle WE# a second time to write the confirm command (lock = 0x01; unlock = 0xD0; lock-

down = 0x2F).

3) Toggle WE# a third time (ex: 0xFF- Read Array) before CE# is deasserted. (See waveform

below.) Any other valid write sequence will also work (i.e., 0x90 - Read Configuration, 0x40 -

Program, 0x20 - Erase).

Status:

16Mb and 64Mb devices on the 0.18µm process are affected. Root cause has been identified and

this erratum may be fixed in a future stepping of the product.

CE#

WE#

0x60

0x2F

CE#

WE#

0x60

0x2F

(0xFF)