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XRT7250 Datasheet(PDF) 140 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 140 Page - Exar Corporation |
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140 / 463 page  áç áç áç áç DS3/E3 FRAMER IC XRT7250 REV. 1.1.1 121 does not issue an Interrupt Acknowledge signal back to the Framer IC. It will just begin processing through the Framer’s interrupt service routine. One the CPU has eliminated the cause(s) of the interrupt request, the Framer’s INT output pin will be negated (e.g., go "High”) and the CPU will return from the Interrupt Ser- vice Routine and resume normal operation. 2.8 INTERFACING THE FRAMER IC TO A MOTOROLA- TYPE MICROPROCESSOR This section discusses how to interface the XRT7250 DS3/E3 Framer IC to the MC68000 Microprocessor. Figure 38 presents a schematic on how to interface the XRT7250 DS3/E3 Framer IC to the MC68000 Mi- croprocessor, over an 8-bit wide bi-directional data bus. In general, the approach to interfacing these two de- vices is pretty straightforward. However, the user must be aware of the fact that the XRT7250 DS3/E3 Framer IC does not provide an interrupt vector to the MC68000 during an Interrupt Acknowledge cycle. Therefore, the user must configure his/her design to support auto-vectored interrupts. Auto-vectored in- terrupt processing is a feature offered by the MC68000 Family of Microprocessors, where, if the microprocessor knows (prior to any IACK cycle) the Interrupt Level of this current interrupt, and that the interrupting peripheral does not support vectored in- terrupts, then the Microprocessor will generate its own Interrupt Vector. The schematic shown in Figure 38, has been configured to support auto-vec- tored interrupts. FIGURE 38. SCHEMATIC DEPICTING HOW TO INTERFACE THE XRT7250 DS3/E3 FRAMER IC TO THE MC68000 MICROPROCESSOR +5V +5V +5V U2 MC68000 RESET 18 R/W 9 DTACK 10 D0 5 D1 4 D2 3 D3 2 D4 1 D5 64 D6 63 D7 62 D8 61 D9 60 D10 59 D11 58 D12 57 D13 56 D14 55 D15 54 A1 29 A2 30 A3 31 A4 32 A5 33 A6 34 A7 35 A8 36 A9 37 FC0 28 FC1 27 FC2 26 VPA 21 IPL0 25 IPL1 24 IPL2 23 AS 6 UDS 7 LDS 8 A10 38 A11 39 A12 40 A13 41 A14 42 A15 43 A16 44 A17 45 A18 46 A19 47 A20 48 A21 49 A22 50 A23 51 U1 XRT7250 RESET 28 WRB_RW 7 Rdy_Dtck 6 D0 32 D1 33 D2 34 D3 35 D4 36 D5 37 D6 38 D7 39 A0 14 A1 15 A2 16 A3 17 A4 18 A5 19 A6 20 A7 21 A8 22 INT 13 CS 8 MOTO/INTEL 27 RDB_DS 10 ALE_AS 9 U4 74AHCT148 0 10 1 11 2 12 3 13 4 1 5 2 6 3 7 4 EI 5 A0 9 A1 7 A2 6 GS 14 EO 15 U5 74AHCT138 A 1 B 2 C 3 G1 6 G2A 4 G2B 5 Y0 15 Y1 14 Y2 13 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 U3 74AHCT138 A 1 B 2 C 3 G1 6 G2A 4 G2B 5 Y0 15 Y1 14 Y2 13 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 U7A 74AHCT04 U7B 74AHCT04 3 4 U6A 74AHCT00 1 2 3 D[15:8] to Address Decoder from Address Decoder Address_Strobe Data_Strobe Address_Strobe Data_Strobe |
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