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XRT7250 Datasheet(PDF) 299 Page - Exar Corporation

Part # XRT7250
Description  DS3/E3 FRAMER IC
PDF  463 Pages
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT7250 Datasheet(HTML) 299 Page - Exar Corporation

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XRT7250
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DS3/E3 FRAMER IC
REV. 1.1.1
280
Table 57 relates the content of this bit-field to the Bi-
polar Line Code that E3 Data will be transmitted and
received at.
NOTES:
1. This bit is ignored if the Unipolar mode is selected.
2. This selection also effects the operation of the
Receive E3 LIU Interface block
5.2.5.2
TxLineClk Clock Edge Selection
The Framer also allows the user to specify whether
the E3 output data (via TxPOS and/or TxNEG output
pins) is to be updated on the rising or falling edges of
the TxLineClk signal. This selection is made by writ-
ing to bit 2 of the I/O Control Register, as depicted be-
low.
Table 58 relates the contents of this bit field to the
clock edge of TxClk that E3 Data is output on the Tx-
POS and/or TxNEG output pins.
NOTE: The user will typically make the selection based
upon the set-up and hold time requirements of the Transmit
LIU IC.
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7BIT 6BIT 5
BIT 4BIT 3BIT2BIT 1BIT 0
Disable TxLOC
LOC
Disable
RxLOC
AMI/ZeroSup*
Unipolar/
Bipolar*
TxLine CLK
Invert
RxLine CLK
Invert
Reframe
R/W
RO
R/W
R/WR/W
R/WR/W
R/W
10
1
00
000
TABLE 57: THE RELATIONSHIP BETWEEN BIT 4 (AMI/
HDB3*) WITHIN THE I/O CONTROL REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT
E3 LIU INTERFACE BLOCK
BIT 4BIPOLAR LINE CODE
0
HDB3
1
AMI
II/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7BIT 6BIT 5BIT 4BIT 3
BIT2BIT 1BIT 0
Disable TxLOC
LOC
Disable
RxLOC
AMI/ZeroSup*
Unipolar/
Bipolar*
TxLine CLK
Invert
RxLine CLK
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
10
100
000
TABLE 58: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 2RESULT
0
Rising Edge:
Outputs on TxPOS and/or TxNEG are updated on the rising edge of TxLineClk.
See Figure 125 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
1
Falling Edge:
Outputs on TxPOS and/or TxNEG are updated on the falling edge of TxLineClk.
See Figure 126 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.



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