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XRT7250 Datasheet(PDF) 321 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 321 Page - Exar Corporation |
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321 / 463 page  XRT7250 áç áç áç áç DS3/E3 FRAMER IC REV. 1.1.1 302 Finally, the Receive E3 Framer block will increment the PMON Parity Error Count registers. The byte for- mat of these registers are presented below. The user can determine the number of BIP-4 Errors that have been detected by the Receive E3 Framer block, since the last read of these registers. These registers are reset-upon-read. Configuring the XRT7250 Framer IC to support BIP-4 Error Detection In order to perform BIP-4 checking of each E3 frame, the user must configure the XRT7250 Framer IC ac- cordingly, by executing the following steps. 1. Configure the Transmit Section (of the XRT7250 Framer IC) to insert the BIP-4 value into the out- bound E3 frames. This is accomplished by writ- ing a “1” into bit-field 7 (Tx BIP-4 Enable) within the TxE3 Configuration Register, as illustrated below. RXE3 INTERRUPT STATUS REGISTER - 2 (ADDRESS = 0X15) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Not Used FERF Interrupt Status BIP-4 Error Interrupt Status Framing Error Interrupt Status Not Used RO RO RO RO RUR RUR RUR RUR 00 000 100 PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Parity Error Count - High Byte RURRUR RUR RUR RURRUR RURRUR 00 000 000 PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Parity Error Count - Low Byte RURRUR RUR RUR RURRUR RURRUR 00 000 000 TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0 Tx BIP-4 Enable TxASourceSel[1:0] TxNSourceSel[1:0] Tx AIS Enable Tx LOS Enable Tx FAS Source Select R/W R/W R/W R/W R/W R/W R/W R/W 10 000 000 |
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