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XRT7250 Datasheet(PDF) 362 Page - Exar Corporation |
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XRT7250 Datasheet(HTML) 362 Page - Exar Corporation |
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362 / 463 page ![]() áç áç áç áç XRT7250 DS3/E3 FRAMER IC REV. 1.1.1 343 connected to the E3_Overhead_Ind, whenever the XRT7250 pulses the TxOH_Ind output pin "High", it will also be driving the E3_Overhead_Ind input pin (of the Terminal Equipment) "High". Whenever the Ter- minal Equipment detects this pin toggling "High", it should delay transmission of the very next E3 frame payload bit by one clock cycle. The behavior of the signals between the XRT7250 and the Terminal Equipment for E3 Mode 2 Operation is illustrated in Figure 160. How to configure the XRT7250 to operate in this mode. 1. Set the NibIntf input pin "Low". 2. Set the TimRefSel[1:0] bit-fields (within the Framer Operating Mode Register) to "01" as depicted below. 3. Interface the XRT7250, to the Terminal Equip- ment, as illustrated in Figure 159. 6.2.1.3 Mode 3 - The Serial/Local-Timed/ Frame-Master ModeBehavior of the XRT7250 If the XRT7250 has been configured to operate in this mode, then the XRT7250 will function as follows. A. Local Timed - Uses the TxInClk signal as the Timing Reference FIGURE 160. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT7250 AND THE TERMINAL EQUIPMENT (MODE 2 OPERATION) Terminal Equipment Signals E3_Clock_In E3_Data_Out Tx_Start_of_Frame E3_Overhead_Ind XRT7250 Transmit Payload Data I/F Signals TxInClk TxSer TxFrame TxOH_Ind Payload[4238] Payload[4239] FA1, Bit 7 FA1, Bit 6 Payload[4238] Payload[4239] FA1, Bit 7 FA1, Bit 6 Note: The FA1 byte will not be processed by the Transmit Payload Data Input Interface. E3 Frame Number N E3 Frame Number N + 1 Note: RxFrame pulses high to denote E3 Frame Boundary. Note: TxOH_Ind pulses high for 16 bit periods in order to denote Overhead Data (e.g., the FA1 and FA2 bytes) FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) BIT 7BIT 6BIT 5BIT 4BIT 3BIT2 BIT 1 BIT 0 Local Loopback DS3/E3* Internal LOS Enable RESET Interrupt Enable Reset Frame Format TimRefSel[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 00 1 0 1 0 0 1 |
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