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TC260 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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TC260 Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 318 page  TC 260 / 264 / 265 / 267 Summary of Features Data Sheet 1-1 V 1.0 2017-06 1 Summary of Features The TC26x product family has the following features: • High Performance Microcontroller with two CPU cores • One 32-bit super-scalar TriCore CPUs (TC1.6P), having the following features: – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Multiply-accumulate unit able to sustain 2 MAC operations per cycle – up to 200 MHz operation at full temperature range – up to 120 Kbyte Data Scratch-Pad RAM (DSPR) – up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR) – 16 Kbyte Instruction Cache (ICACHE) – 8 Kbyte Data Cache (DCACHE) • Power Efficient scalar TriCore CPU (TC1.6E), having the following features: – Binary code compatibility with TC1.6P – up to 200 MHz operation at full temperature range – up to 72 Kbyte Data Scratch-Pad RAM (DSPR) – up to 16 Kbyte Instruction Scratch-Pad RAM (PSPR) – 8 Kbyte Instruction Cache (ICACHE) – 0.125Kbyte Data Read Buffer (DRB) • Lockstepped shadow core for TC1.6P • Multiple on-chip memories – All embedded NVM and SRAM are ECC protected – up to 2.5 Mbyte Program Flash Memory (PFLASH) – up to 96 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 0 Kbyte Memory (LMU) – BootROM (BROM) • 48-Channel DMA Controller with safe data transfer • Sophisticated interrupt system (ECC protected) • High performance on-chip bus structure – 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between busmasters, CPUs and memories – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – One bus bridge (SFI Bridge) • Safety Management Unit (SMU) handling safety monitor alarms • Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU) • Hardware I/O Monitor (IOM) for checking of digital I/O • Versatile On-chip Peripheral Units – Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud – Four Queued SPI Interface Channels (QSPI) with master and slave capability upto 50 Mbit/s – High Speed Serial Link (HSSL) for serial inter-processor communication up to 320Mbit/s |
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