RT1020 datasheet(96/97 Pages) NXP

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i.MX RT1020 Crossover Processors for Industrial Products, Rev. 1, 04/2019

NXP Semiconductors

Revision history

Table 86 provides a revision history for this data sheet.

Table 86. i.MX RT1020 data sheet document revision history

Rev.

Number

Date

Substantive Change(s)

Rev. 1

04/2019

• Added analog descriptions in the Section 1.1, Features

• Added ADC channel number in the Table 1, The comparison between 100 LQFP and 144 LQFP

package

• Updated the RT website link in the Section 1.2, Ordering information

• Updated the ADC descriptions in the Figure 2, "i.MX RT1020 system block diagram"

• Updated the RAM size, SNVS descriptions, and USB descriptions in the Table 3, i.MX RT1020

modules list

• Updated the on-chip termination values of JTAG_TCK and JTAG_MOD in the Table 5, JTAG controller

interface summary

• Updated the maximum values of VDD_SOC_IN in the Table 8, Absolute maximum ratings

• Removed the USB_OTG2_VBUS from the Table 8, Absolute maximum ratings, Table 11, Operating

ranges, and Section 4.2.1.1, Power-up sequence

• Changed 528 MHz PLL to System PLL in the Table 17, System PLL’s electrical parameters

• Changed 480 MHz PLL to USB PLL in the Table 19, USB PLL’s electrical parameters

• Updated the Section 4.8.1, LPSPI timing parameters

• Added the Figure 32, "Minimum Sample Time Vs Ras (Cas = 2pF)", Figure 33, "Minimum Sample

Time Vs Ras (Cas = 5 pF)", and Figure 34, "Minimum Sample Time Vs Ras (Cas = 10 pF)" in the

Section 4.7.2, A/D converter

Rev. 0.1

07/2018

• Updated the Table 14, Low power mode current and power consumption

• Added the Section 4.4.4, Debug trace timing specifications

Rev. 0

06/2018

• Initial version

RT1020 Datasheet(PDF) 96 Page - NXP Semiconductors