VSC7440 datasheet(249/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

232

The front ports are connected to taxi busses and must be guaranteed bandwidth that corresponds to their

line speed. The internal CPU ports and loopback paths can operate up to 10 Gbps (7.5 Gbps for VD0).

In any port configuration, a subset of the ports is enabled. The calendar algorithm is the central place

where bandwidth is distributed between the ports. The calendar algorithm can be controlled by two

methods: automatic or sequenced.

In the automatic calendar configuration, a configuration per port defines if the port is granted 0 Gbps,

1 Gbps, 2.5 Gbps, or 10 Gbps bandwidth. For the four internal ports, the bandwidth granted is half of

these choices. In other words, internal CPU port 1 can be granted 1.25 Gbps in bandwidth.

In the sequenced operation, a specific sequence of port numbers forms the calendar. The port sequence

controls which port is granted the cycle, per bus cycle (two system clock periods).

The algorithm mode is configured in CAL_CTRL.CAL_MODE. It is possible through this register to

program a manual sequence, to halt the calendar, and to select between sequenced and automatic

calendars.

Both calendar modes may leave some slots unallocated and therefore idle on the busses. These idle

cycles can be used for configuration access (which will wait for unused cycles) and other slow operations

in the system (MAC table scan, for example). Slots allocated for a port and not used due to lack of data to

transfer can be used by the internal ports through the HSCH::OUTB_* registers, where it is, per internal

port, configured how often it will seek granting of an unused cycle. Setting internal CPU port 0 to seek

access every five cycles means that it can get up to one frame transfer every 64 ns, or approximately

10 Gbps.

In the ingress side, the loopback paths can use idle cycles if enabled in the assembler, which controls the

ingress mux.

The following table list the registers associated with configuring the calendar function.

3.25

Automatic Frame Injector

The automatic frame injector (AFI) provides mechanisms for periodic injection of PDUs such as 1588

PDUs. The following blocks are involved in frame injection.

•

QSYS - The frames are sent into the queue system by the CPU and stored in the queue system until

deleted by software.

•

AFI - Using timers and other parameters, AFI controls the automatic frame injection.

•

REW - For outbound data path injections, the REW performs frame modifications.

•

Loopback path - The loopback path (VD1) between the disassembler and assembler is used to

inject frames into the inbound data path.

•

ANA - For inbound data path injections, the ANA performs modifications of frames.

AFI supports two types of automatic frame injection: timer triggered (TTI) and delay triggered (DTI).

•

Timer Triggered Injection (TTI) - Frame injection rate is controlled by timers with typical values of

approximately 3 ms or higher. Only single-frame injections are supported; injection of sequences of

frames is not supported. For each frame, jitter can be enabled for the associated injection timer.

Timer triggered injection can be combined with delay triggered injection.

Table 160 •

Calendar Registers Overview

Description

CAL_CTRL

Calendar function mode. Configures auto-grant rate.

OUTB_SHARE_ENA

Enables granting unused bus cycles to the internal ports (CPU and VD)

on the egress side.

OUTB_CPU_SHARE_ENA

Configures bandwidth sharing between the two internal CPU ports.

CAL_SEQ

Interface to the sequence memory. See register list.

CAL_AUTO

Per port setting with requested bus bandwidth.

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