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VSC7440 Datasheet(PDF) 248 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 248 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
231
To read number of transmitted yellow frames for service counter 714:
1.
Write 714 to STAT_VIEW in QSYS::STAT_CFG.
2.
Read QSYS::CNT[385].
To read number of discarded green octets with QoS class 4 on port 9:
1.
Write 9 to STAT_VIEW in QSYS::STAT_CFG.
2.
Read QSYS::CNT[76] for the least significant bits.
3.
Read QSYS::CNT[140] for the most significant bits.
3.24.9.5 Energy Efficient Ethernet (EEE) Control
The front ports are able to signal low power idle (LPI) towards the MACs, in case they request the PHYs
to enter low power mode. A controller in each port module assures that frames are not transmitted when
the PHYs are powered down. This controller powers the PHY down when there is nothing to transmit for
a while, and it powers up the PHY when there is either data ready for a configurable time or when the
queue system has urgent data ready requiring transmission as soon as possible.
The following table lists the registers with configuring EEE.
Example: Configure the device to power up the PHYs when 10 frames are pending.
Only ports 3 through 6 should regard their data as urgent and only for priorities 6 and 7. All other data
should get transmitted when the EEE controller in the port has seen pending data for the controller
configured time.
1.
Write 10 to QSYS::EEE_THRES:EEE_HIGH_FRAMES.
2.
Write 0xC0 to QSYS::EEE_CFG[3–6]::EEE_FAST_QUEUES.
3.24.9.6 Calendar Setup
There are a number of logical ports, all needing bandwidth into and out of the queue system. This is
controlled through a calendar module that grants each port access to internal busses.
The following illustration shows an overview of the internal busses. All ports are connected to a port data
bus (taxi bus) and granted access to the chip core through a mux obeying the calendar decision.
Similarly, on the path towards the transmit interface, a mux controls which port transmits the next time.
Figure 69 •
Internal Bus
Table 159 •
EEE Registers Overview
Register
Description
Replication
QSYS::EEE_CFG
Configures the priorities per port which should bring the port
alive as fast as possible.
Per port
QSYS::EEE_THRES
Configures the amount of cells or frames pending for a priority
before the port should request immediate power up.
Per port
Front
Ports
Front
Ports
Queues
Loopback VD0/VD1
TAXI_CPU
Calendar
Algorithm
TAXI_0
...
TAXI_CPU
TAXI_0
...



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