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VSC7440 Datasheet(PDF) 244 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 244 Page - Microsemi Corporation

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Functional Descriptions
VMDS-10492 VSC7440 Datasheet Revision 4.2
227
•
Data rate shapers are connected in a linked list, which is traversed every 10 µs. The shaper rate
granularity becomes 100 kbps.
•
Frame rate shapers are connected in a linked list, which is traversed every 1 ms. The shaper rate
granularity becomes 1 kilo frames per second.
Each scheduler element includes two leaky buckets to support DLB shaping. The committed information
rate (CIR) bucket is open when the filling is below the configured limit. The excess information rate (EIR)
shaper is always closed, unless the congestion control reports that a threshold is reached. Which
congestion thresholds to react on are configurable for each shaper and should depend on the traffic
groups the particular element is a part of. The effect of the DLB shaper is that the rate out of the shaper
is CIR or CIR plus EIR, depending of the accumulation of data in the queue system.
The following table lists the registers associated with shaping.
3.24.7.4 Bandwidth Distribution
Each scheduler element is selecting one of its inputs as the next source of transmission if a scheduling
process passes through it. A number of different options are available for how this arbitration takes place.
A configured value for the scheduler element tells how many of the lower indexed inputs should be
arbitrated with the DWRR method. Inputs with higher indexes are preferred and arbitrated strict.
Figure 68 •
Scheduler
The lower indexes are arbitrated in the effort to achieve a bandwidth ratio between them. In this regard,
the bandwidth can be measured in frames, data bits, or line bits (including IFG). Each input is configured
with a cost setting, and the algorithm strives to give n times more bandwidth to input A than B, if the cost
configuration for A is n times lower than B. The following are two cost configuration examples.
•
Input 4 has cost 7, and input 6 has cost 11. If the total bandwidth shaped out of the scheduler
element is 180 Mbps, input 4 will get 110 Mbps of it.
•
All inputs have cost 1, and the element is configured for frames per second arbitration. Algorithm will
by this strive to send an equal number of frames from each input.
Table 153 •
Shaper Registers Overview
Register
Description
HSCH::SE_CFG
Selects filling mode
HSCH::CIR_CFG
Configures leak rate and burst capacity for CIR bucket
HSCH::EIR_CFG
Configures leak rate and burst capacity for EIR bucket
HSCH::SE_DLB_SENSE
Selects thresholds to control EIR with.
HSCH::HSCH_LEAK_LIST
Configures leak list periods and starting index
HSCH::SE_CONNECT
Links to next in leaking lists
HSCH::CIR_STATE
Returns current CIR bucket filling
HSCH::EIR_STATE
Returns current EIR bucket filling
HSCH::SE_STATE
Returns whether or not the shaper is open
0
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