VSC7440 datasheet(311/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

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The state transition timing values are configured in the EEE_CFG register per port module, and the

levels at which the queue system asserts forward pressure are configured in the QSYS::EEE_CFG and

QSYS::EEE_THRES registers.

As illustrated, the “port has frames for transmission” condition is true if there are frames for transmission

and the scheduling algorithm allows transmission of any of the available frames. So it is possible that a

port enters LPI_EMPTY or stays in LPI_EMPTY, even though there are frames in one or more queues.

It is also possible, though not likely, that forward pressure is set for one or more queues when going into

LPI_EMPTY. This occurs when the scheduling algorithm has decided to transmit from other queue or

queues than those signalling forward pressure and the transmission of these frames causes the port

leaky bucket to close.

The “forward pressure signalled for queues” condition does not look at whether the queues with forward

pressure are actually allowed to transmit.

For ports that are shaped to a low bandwidth, the forward pressure watermark in OQS should be set a

low value, such that it is mainly the port shaping that controls when to exit LPI.

3.32

CPU Injection and Extraction

This section provides an overview of how the CPU injects and extracts frames to and from the switch

core.

The switch core forwards CPU extracted frames to eight CPU extraction queues that per queue are

mapped to one of the two CPU ports (by means of QFWD:SYSTEM:FRAME_COPY_CFG[0:7]) that the

CPU can access. For each CPU extraction queue, it is possible to specify the egress priority

(QFWD:SYSTEM:FRAME_COPY_CFG.FRMC_QOS_ENA). For each CPU port, there is strict priority

selection between the egress queues.

For injection, there are two CPU injection groups that can simultaneously forward frames into the

analyzer. The CPU can access the injection and extraction groups through either a Frame DMA or direct

For more information about injecting and extracting CPU traffic through front ports used as NPI port, see

Internal Frame Header Placement, page 13; Setting Up a Port for Frame Injection, page 51; and

Forwarding to GCPU, page 267.

3.32.1

Frame Injection

The traffic at any injection pipeline point from CPU, NPI, and AFI using the IFH

(IFH.MISC.PIPELINE_ACT:= INJ_MASQ and IFH.MISC.PIPELINE_PT: = <value>).

When a frame is injected at a given pipeline point, it is logically not processed in the flow before reaching

the injection point. For example, a frame injected at the ANA_CLM pipeline point bypasses VRAP

detection, port Down-MEP handling, and basic classification, which requires the frame to be injected with

an IFH configured with all the fields normally set by Basic classification.

Injecting a frame at the ANA_DONE pipeline point causes it to bypass the complete analyzer and

destination port must be specified in IFH (IFH.MISC.DPORT = <egress port>).

Frames can be injected as either unicast or as multicast:

•

Unicast injection that allows injection into a single egress port (configured in IFH.MISC.DPORT) with

all IFH.DST.ENCAP operators available in the Rewriter such as OAM and PTP detection and

hardware handling (if IFH.FWD.DST_MODE is set to ENCAP).

•

Multicast injection that allows injection to multiple egress ports (IFH.FWD.DST_MODE = INJECT

and IFH.DST.INJECT.PORT_MASK). Because IFH.DST is used for specifying the destination set, it

is not possible to use IFH.DST.ENCAP for this type of injection and all IFH.DST.ENCAP fields will

default to 0. This mode bypasses the analyzer, meaning that all IFH fields used by rewriter must be

given a proper value by software.

3.32.1.1 Masqueraded Injection

The device supports masqueraded injection of frames from CPU where processing of the frame is done

as if the frame was received on the masqueraded port (IFH.MISC.PIPELINE_ACT=INJ_MASQ and

VSC7440 Datasheet(PDF) 311 Page - Microsemi Corporation

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