VSC7440 datasheet(312/444 Pages) MICROSEMI

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Functional Descriptions

VMDS-10492 VSC7440 Datasheet Revision 4.2

295

IFH.FWD.SRC_PORT=<masqueraded port>). A masquerade-injected frame sees the same source filter,

classification, and learning as the physical port being masqueraded.

3.32.1.2 Injection Pipeline Points

The device supports specifying where in the processing flow a frame is injected by specifying a pipeline

point for the frame (IFH.MISC.PIPELINE_PT0). The frame will then only be processed after the specified

injection point.

3.32.2

Frame Extraction

The CPU receives frames through eight CPU extraction queues. These extraction queues can be

mapped to one of the two CPU ports or any of the front ports (QFWD:SYSTEM:FRAME_COPY_CFG[0-

7]). The CPU extraction queues use memory resources from the shared queue system and are subject to

the thresholds and congestion rules programmed for the CPU extraction queues and the shared queue

system in general.

A frame can be extracted for multiple reasons. For example, a BPDU with a new source MAC address

can be extracted as both a BPDU and a learn frame with two different CPU extraction queues selected.

By default, the highest CPU extraction queue number receives a copy of the frame, but it is also possible

to generate multiple frame copies to all the selected CPU extraction queues

(ANA_AC::CPU_CFG.ONE_CPU_COPY_ONLY_MASK).

The CPU can read frames from the CPU port in two ways:

•

Reading registers in the CPU system. For more information, see Manual Extraction, page 331.

•

Using the Frame DMA in the CPU system. For more information, see FDMA Extraction, page 330.

CPU extracted frames include an IFH (28-bytes) placed in front of the DMAC. The IFH contains relevant

side band information about the frame, such as the frame’s classification result (VLAN tag information,

DSCP, QoS class) and the reason for sending the frame to the CPU. For more information about the

contents of the IFH, Frame Headers, page 13.

The originating CPU extraction port number is not part of the IFH, however, a 4-byte header can be

included in front of the IFH containing the CPU extraction port number

(DEVCPU_QS::XTR_GRP_CFG.MODE).

3.32.3

Forwarding to CPU

Several mechanisms can be used to trigger redirection or copying of frames to the CPU. The following

blocks can generate traffic to a CPU queue.

•

Analyzer classifier ANA_CL

•

Analyzer Layer 3 ANA_L3

•

Analyzer Access Control Lists ANA_ACL

•

Analyzer Layer 2 ANA_L2

•

Analyzer Access Control ANA_AC

•Rewriter

Frames copied or redirected to the CPU from both the rewriter and the Up-MEPs are looped and passed

another time through the analyzer.

3.32.4

Automatic Frame Injection (AFI)

The AFI block supports repeated (automated) injection, which requires the injection frame to be sent to

the AFI block with a single IFH bit set (IFH.FWD.AFI_INJ) and with an IFH header configured as for

normal CPU injection.

After an injection frame is sent to the AFI block, the frame can be added for AFI injection. For more

information, see Adding Injection Frame, page 244.

Frames injected from the AFI block are treated as any CPU injection, where IFH fields controls how

injection occurs.

A Down-MEP injected frame must be directly injected into the right egress port as shown in the following

illustration.

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