VSC7440 datasheet(388/444 Pages) MICROSEMI

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Electrical Specifications

VMDS-10492 VSC7440 Datasheet Revision 4.2

371

Electrical Specifications

This section provides the DC characteristics, AC characteristics, recommended operating conditions,

and stress ratings for the VSC7440 device.

6.1

DC Characteristics

This section contains the DC specifications for the VSC7440 device.

6.1.1

Reference Clock

The following table lists the DC specifications for the differential reference clock signals. Differential and

single-ended modes are supported.

6.1.2

PLL Clock Output

The following table lists the DC specifications for the PLL clock outputs. Applies to CLKOUTPLL and

CLKOUTPLL2 pins.

6.1.3

DDR3/DDR3L SDRAM Interface

This section provides the DC specifications for the DDR3 and DDR3L interfaces.

The DDR3 SDRAM interface supports the requirements of SDRAM devices as described in the JEDEC

DDR3 specifications. The SDRAM interface signals are compatible with JESD79-3F (DDR3 SDRAM

SPECIFICATION, July 2012) and JESD79-3-1A, January 2013. The SSTL I/O buffers have

programmable on-die termination (ODT).

Table 275 •

Reference Clock Inputs

Parameter

Symbol

Minimum

Typical

Maximum

Unit

Input voltage range

VIP, VIN

–25

1200

Single-ended input swing

|VSE|

600

10001

Input common-mode voltage and amplitude must not exceed 1200 mV.

Differential peak-to-peak input swing

|VID|

200

1200

mVppd

Input common-mode voltage

VCM

2/3 ×VDD

Table 276 •

PLL Clock Output

Parameter

Symbol

Minimum

Typical Maximum Unit

Condition

Differential resistance

RDIFF

100

120

Differential peak-to-peak output swing

VOD

290

510

mVppd

Differential peak-to-peak output swing

VOD

360

635

mVppd

See note 1.

Driver amplitude depends on driver-to-receiver adaptation configured in register. Increased amplitude can be

achieved if the receiver is common-mode terminated to VDD_A and if the driver is configured accordingly.

Output common-mode voltage

VCM

VDD_A – 500 mV

VDD_A

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