VSC7440 datasheet(384/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

367

The following table lists the available interrupt destinations in the device.

All interrupts, events, and indications inside in the interrupt controller are active high. If an interrupt

source supports polarity correction, it is applied before going into the interrupt controller. If an interrupt

destination supports polarity correction, it is applied after leaving the interrupt controller.

4.8.13.1 Interrupt Source Configuration

Interrupt sources are handled identically inside the interrupt controller. This section describes interrupt

source n, which refers to the bit index of that interrupt source in the INTR_* and DST_INTR_* registers.

The following illustration shows the logic associated with a single interrupt source.

Figure 130 •

Interrupt Source Logic

The current value of an interrupt source is available in INTR_RAW.INTR_RAW[n].

INTR_STICKY.INTR_STICKY[n] is set when the interrupt controller detects an interrupt. There are two

detection methods:

•

When INTR_TRIGGER.INTR_TRIGGER[n] is set to level-activated, the interrupt controller

continually sets INTR_STICKY.INTR_STICKY[n] for as long as the interrupt source is active.

•

When INTR_TRIGGER.INTR_TRIGGER[n] is set to edge-triggered, the interrupt controller only sets

INTR_STICKY.INTR_STICKY[n] when the interrupt source changes value.

•

When INTR_TRIGGER.INTR_TRIGGER[n] is set to falling-edge-triggered, the interrupt controller

only sets INTR_STICKY.INTR_STICKY[n] when the interrupt source changes from active to inactive

value.

•

When INTR_TRIGGER.INTR_TRIGGER[n] is set to rising-edge-triggered, the interrupt controller

only sets INTR_STICKY.INTR_STICKY[n] when the interrupt source changes from inactive to active

value.

Software can clear INTR_STICKY.INTR_STICKY[n] by writing 1 to bit n. However, the interrupt controller

will immediately set this bit again if the source input is still active (when INTR_TRIGGER is 0) or if it sees

a triggering event on the source input (when INTR_TRIGGER different from 0).

The interrupt source is enabled in INTR_ENA.INTR_ENA[n]. When INTR_STICKY.INTR_STICKY[n] is

set and the interrupt is enabled, the interrupt is indicated towards the interrupt destinations. For more

Table 273 •

Interrupt Destinations

Destination Name

Description

CPU0

Interrupt 0 to VCore-III CPU. This interrupt has replication index 0 in

DST_INTR_* registers.

CPU1

Interrupt 1 to VCore-III CPU. This interrupt has replication index 1 in

DST_INTR_* registers.

EXT_DST0

External interrupt destination 0. See External Interrupts. This interrupt has

replication index 2 in DST_INTR_* registers.

EXT_DST1

External interrupt destination 1. See External Interrupts. This interrupt has

replication index 3 in DST_INTR_* registers.

Filter Logic

00 Pass any.

01 Detect change.

10 Active to inactive.

11 Inactive to active.

INTR_TRIGGER.INTR_TRIGGER[n]

Interrupt Source n

Sticky

Hold interrupt

indication until

cleared by SW

INTR_STICKY.INTR_STICKY[n]

INTR_BYPASS.INTR_BYPASS[n]

INTR_ENA.INTR_ENA[n]

INTR_IDENT.INTR_IDENT[n]

To destination logic

AND

INTR_RAW.INTR_RAW[n]

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