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VSC7440 Datasheet(PDF) 381 Page - Microsemi Corporation |
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VSC7440 Datasheet(HTML) 381 Page - Microsemi Corporation |
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381 / 444 page ![]() VCore-III System and CPU Interfaces VMDS-10492 VSC7440 Datasheet Revision 4.2 364 Figure 129 • Memory Detection Logic If the MEM_ERR_OVF or MEM_COR_OVF flag is set, at least one event has occurred for which the address could not be stored. The following table shows ECC-enabled memories in the device, their index, and the recommended approach for handling indications. If the controller reports an index that is not mentioned in the list, the recommended approach is to reboot the device. The VCore-III CPU implements parity protection of all VCore-III cache structures as specified by MIPS architecture. For information about how to enable parity protection and interrupt on parity upsets, see the MIPS documentation. Reading from uninitialized memory locations has a high plausibility of triggering non correctable or correctable indications. This is useful when developing integrity monitor software driver. For example, powering up a system without initializing the VCAPs and reading actions and sticky bits will trigger monitor indications. Note that the contents of memories are not changed by device reset, so power cycle is needed to reset the memories. 4.8.13 Interrupt Controller This section provides information about the VCore-III interrupt controller. Table 270 • Memories with Integrity Support Index Description Others For unlisted indexes, the recommended approach is to reboot the device. Upset is detected Is upset correctable? Is MEM_ERR set? Save upset address to: MEM_ADDR Set MEM_ERR Set MEM_ERR_OVF Is MEM_ERR set? Is MEM_COR set? Save upset address to: MEM_ADDR Set MEM_COR Set MEM_COR_OVF yes yes yes yes no no no no Is monitor in LISTEN state? yes no Is upset correctable? yes no Set MEM_ERR_OVF Set MEM_COR_OVF |
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