VSC7440 datasheet(377/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

360

edge-triggered, falling-edge-triggered, and rising-edge-triggered interrupt. This register is a sticky bit

vector and can only be cleared by software. A bit is cleared by writing a 1 to the bit position.

•

SIO_INTR_IDENT is the result of SIO_INTR with the disabled interrupts (from SIO_INTR_ENA and

SIO_GPIO_INTR_ENA) removed. This register changes when SIO_INTR or the enable registers

change.

The SIO controller has one interrupt output connected to the main interrupt controller, which is asserted

when one or more interrupts in SIO_INTR_IDENT are active. To determine which SGPIO is causing the

interrupt, the CPU must read this register. The interrupt output remains high until all interrupts in

SIO_INTR_IDENT are cleared (either by clearing SIO_INTR or disabling the interrupts in

SIO_INTR_ENA and SIO_GPIO_INTR_ENA).

4.8.9.3

Loss of Signal Detection

The SIO controller can propagate loss of signal detection inputs directly to the signal detection input of

the port modules. This is useful when, for example, SFP modules are connected to the device. The

mapping between SIO ports and port modules is the same as for the link activity outputs; port 0 is

connected to port module 0, port 1 is connected to port module 1, and so on.

The value of SGPIO bit 0 of each SIO port is forwarded directly to the loss of signal input on the

corresponding port module. The port module must enable the loss of signal input locally.

Loss of signal can also be taken directly from overlaid functions on the regular GPIOs. In that case, the

input from the SIO controller is ignored.

The polarity of the loss of signal input is configured using SIO_INT_POL, meaning the same polarity

must be used for loss of signal detect and interrupt.

4.8.10

Fan Controller

The device includes a fan controller that can be used to control and monitor a system fan. A pulse width

modulation (PWM) output regulates the fan speed. The fan speed is monitored using a TACHO input.

The fan controller is especially powerful when combined with the internal temperature sensor. For more

information, see Temperature Sensor, page 361.

The following table lists the registers associated with the fan controller.

The following table lists fan controller pins, which are overlaid on GPIOs. For more information about

overlaid functions on the GPIOs for these signals, see GPIO Overlaid Functions, page 352.

The PWM output can be configured to any of the following frequencies in FAN_CFG.PWM_FREQ:

10 Hz, 20 Hz, 40 Hz, 60 Hz, 80 Hz, 100 Hz, 120 Hz, or 25 kHz.

The low frequencies can be used for driving three-wire fans using a FET/transistor. The 25 kHz

frequency can be used for four-wire fans that use the PWM input internally to control the fan. The duty

cycle of the PWM output is programmable from 0% to 100%, with 8-bit accuracy. The polarity of the

output can be controlled by FAN_CFG.INV_POL, so a duty-cycle of 100%, for example, can be either

always low or always high.

Table 266 •

Fan Controller

Description

DEVCPU_GCB::FAN_CFG

General configuration

DEVCPU_GCB::FAN_CNT

Fan revolutions counter

Table 267 •

Fan Controller Pins

I/O

Description

TACHO/GPIO

TACHO input for counting revolutions

PWM/GPIO

PWM fan output

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