VSC7440 datasheet(373/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

356

If the SIO controller is only used for outputs, the use of the load signal is optional. If the load signal is

omitted, simpler shift registers (without load) can be used, however, the outputs of these registers will

toggle during shifting.

When driving LED outputs, it is acceptable that the outputs will toggle when SGPIO values are updated

(shifted through the chain). When the shift frequency is fast, the human eye is not able to see the shifting

though the LEDs.

The number of shift registers in the chain is configurable. The SIO controller allows enabling of individual

ports through SIO_PORT_ENA; only enabled ports are shifted out on SG0_DO. Ports that are not

enabled are skipped during shifting of GPIO values.

Note: SIO_PORT_ENA allows skipping of ports in the SGPIO output stream that are not in use. The number of

GPIOs per (enabled) port is configurable as well, through SIO_CFG.SIO_PORT_WIDTH this can be set

to 1, 2, 3, or 4 bits. The number of bits per port is common for all enabled ports, so the number of shift

registers on the PCB must be equal to the number of enabled ports times the number of SGPIOs per

port.

Enabling of ports and configuration of SGPIOs per port applies to both output mode and input mode.

Unlike a regular GPIO port, a single SGPIO position can be used both as output and input. That is,

software can control the output of the shift register AND read the input value at the same time. Using

SGPIOs as inputs requires load-capable shift registers.

Regular shift registers and load-capable shift-registers can be mixed, which is useful when driving LED

indications for integrated PHYs while supporting reading of link status from SFP modules, for example.

Figure 124 •

SIO Timing

The SGPIO values are output in bursts followed by assertion of the SG0_LD signal. Values can be output

as a single burst or as continuous bursts separated by a configurable burst gap. The maximum length of

a burst is 32 × 4 data cycles. The burst gap is configurable in steps of approximately 1 ms, from 0 ms to

33 ms through SIO_CFG.SIO_BURST_GAP_DIS and SIO_CFG.SIO_BURST_GAP.

A single burst is issued by setting SIO_CFG.SIO_SINGLE_SHOT. The field is automatically cleared by

hardware when the burst is finished. To issue continuous bursts, set SIO_CFG.SIO_AUTO_REPEAT.

The SIO controller continues to issue bursts until SIO_CFG.SIO_AUTO_REPEAT is cleared.

SGPIO output values are configured in SIO_PORT_CFG.BIT_SOURCE. The input value is available in

SIO_INPUT_DATA.

The following illustration shows what happens when the number of SGPIOs per port is configured to two

(through SIO_CFG.SIO_PORT_WIDTH). Disabling ports (through SIO_PORT_ENA) is handled in the

same way as disabling the SGPIO ports.

pN-1

SG0_DO

SG0_DI

SG0_CLK

SG0_LD

Serial to parallel shift registers output

data on rising edge

Parallel to serial shift registers load

data on logical 0

28 ns

pN-1

Burst gap

VSC7440 Datasheet(PDF) 373 Page - Microsemi Corporation

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