VSC7440 datasheet(376/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

359

The link activity mode uses an envelope signal to gate the selected blinking pattern (blink mode 0 or blink

mode 1). When the envelope signal is asserted, the output blinks, and when the envelope pattern is de-

asserted, the output is turned off. To ensure that even a single packet makes a visual blink, an activity

pulse from the port module is extended to minimum 100 ms. If another packet is sent while the envelope

signal is asserted, the activity pulse is extended by another 100 ms. The polarity of the link activity

modes can be set in SIO_PORT_CFG.BIT_SOURCE.

The following illustration shows the link activity timing.

Figure 127 •

Link Activity Timing

4.8.9.2

SIO Interrupt

The SIO controller can generate interrupts based on the value of the input value of the SGPIOs. All

interrupts are level sensitive.

Interrupts are enabled using the two registers. Interrupts can be individually enabled for each port in

SIO_INTR_ENA (32 bits) and in SIO_CFG.SIO_GPIO_INTR_ENA (4 bits) interrupts are enabled for the

four inputs per port. In other words, SIO_CFG.SIO_GPIO_INTR_ENA is common for all 32 ports.

The SIO controller has four interrupt registers that each has one bit for each of the 128 GPIOs:

•

SIO_INTR_RAW is high if the corresponding input bit is high (corrected for polarity as configured in

SIO_INTR_POL). This register changes when the input changes.

•

SIO_INTR is high if the condition of the configured trigger mode for the bit is met. The trigger mode

can be configured in SIO_INTR_TRIGGER0 and SIO_INTR_TRIGGER1 between level-triggered,

Free

Table 265 •

SIO Controller Port Mapping (continued)

SIO Port

SG0 Mapping

100 ms pulse

MAC pulse

Envelope

Blink mode

Output

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