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VSC7440 Datasheet(PDF) 374 Page - Microsemi Corporation |
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VSC7440 Datasheet(HTML) 374 Page - Microsemi Corporation |
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374 / 444 page  VCore-III System and CPU Interfaces VMDS-10492 VSC7440 Datasheet Revision 4.2 357 Figure 125 • SIO Timing with SGPIOs Disabled The frequency of the SG0_CLK clock output is configured through SIO_CLOCK.SIO_CLK_FREQ. The SG0_LD output is asserted after each burst; this output is asserted for a period of 25 ns to 30 ns. The polarity of SG0_LD is configured in SIO_CFG.SIO_LD_POLARITY. The SG0_LD output can be used to ensure that outputs are stable when serial data is being shifted through the registers. This can be done by using the SG0_LD output to shift the output values into serial- to-parallel registers after the burst is completed. If serial-to-parallel registers are not used, the outputs will toggle while the burst is being shifted through the chain of shift registers. A universal serial-to-parallel shift register outputs the data on a positive-edge load signal, and a universal parallel-to-serial shift register shifts data when the load pin is high, so one common load signal can be used for both input and output serial parallel conversion. The assertion of SG0_LD happens after the burst to ensure that after power up, the single burst will result in well-defined output registers. Consequently, to sample input values one time, two consecutive bursts must be issued. The first burst results in the input values being sampled by the serial-to-parallel registers, and the second burst shifts the input values into the SIO controller. The port order required in the serial bitstream depends on the physical layout of the shift register chain. Often the input and output port orders must be opposite in the serial streams. The port order of the input and output bitstream is independently configurable in SIO_CFG.SIO_REVERSE_INPUT and SIO_CFG.SIO_REVERSE_OUTPUT. The following illustration shows the port order. Figure 126 • SGPIO Output Order 4.8.9.1 Output Modes The output mode of each SGPIO can be individually configured in SIO_PORT_CFG.BIT_SOURCE. The SIO controller features three output modes: • Static • Blink • Link activity pN-2 b1 pN b3 SG0_DO SG0_CLK SG0_LD pN b2 pN b1 pN b0 p0 b3 p0 b2 p0 b1 p0 b0 Burst pN-1 b3 pN-1 b2 pN-1 b1 pN-1 b0 pN-2 b3 pN-2 b2 Disabled Disabled Disabled Disabled pN b3 SG0_CLK pN b2 pN b1 pN b0 pN-1 b3 p0 b3 p0 b2 p0 b1 p0 b0 p0 b0 p0 b1 p0 b2 p1 b1 p0 b3 p1 b0 p2 b0 pN b0 pN b1 pN b2 pN b3 pN-2 b3 pN-1 b0 pN-1 b1 pN-1 b2 p1 b2 p1 b2 p1 b3 pN b3 pN b2 pN b1 pN b0 pN-1 b3 p0 b3 p0 b2 p0 b1 pN b3 p0 b0 p0 b1 p0 b2 p1 b1 p0 b3 p1 b0 p2 b0 pN b0 pN b1 pN b2 p0 b0 pN-2 b3 pN-1 b0 pN-1 b1 pN-1 b2 p1 b2 p1 b2 p1 b3 SG0_DO SG0_DI Reverse order Default order SG0_DO SG0_DI |
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