VSC7440 datasheet(369/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

352

value during scanning, and the mask register has a 1 for the corresponding bit, a mismatch for the PHY

is registered.

The scan results from the most recent scan can be read in MII_SCAN_LAST_RSLTS. The register

contains one bit for each of the possible 32 PHYs. A mismatch during scanning is indicated by a 0.

MII_SCAN_LAST_RSLTS_VLD will indicate for each PHY if the read operation performed during the

scan was successful. The sticky-bit register MII_SCAN_RSLTS_STICKY has the mismatch bit set for all

PHYs that had a mismatch during scanning since the last read of the sticky-bit register. When the register

is read, its value is reset to all-ones (no mismatches).

4.8.7.4

MII Management Interrupt

The MII management controllers can generate interrupts during PHY scanning. Each MII management

controller has a separate interrupt signal to the interrupt controller. Interrupt is asserted when one or

more PHYs have a mismatch during scan. The interrupt is cleared by reading the

MII_SCAN_RSLTS_STICKY register, which resets all MII_SCAN_RSLTS_STICKY indications.

4.8.8

GPIO Controller

This section provides information about the use of GPIO pins.

The following table lists the registers associated with GPIO.

The GPIO pins are individually programmable. GPIOs are inputs by default and can be individually

changed to outputs through GPIO_OE. The value of the GPIO pins is reflected in the GPIO_IN register.

GPIOs that are in output mode are driven to the value specified in GPIO_OUT.

In a system where multiple different CPU threads (or different CPUs) may work on the GPIOs at the

same time, the GPIO_OUT_SET and GPIO_OUT_CLR registers provide a way for each thread to safely

control the output value of individual GPIOs, without having to implement locked regions and

semaphores.

The GPIO_ALT registers are only reset by external reset to the device. This means that software reset of

the DEVCPU_GCB is possible without affecting the mapping of overlaid functions on the GPIOs.

4.8.8.1

GPIO Overlaid Functions

Most of the GPIO pins have overlaid (alternative) functions that can be enabled through replicated

GPIO_ALT registers.

To enable a particular GPIO pin with the alternate function, set the G_ALT[n] register field in the

replicated registers as follows:

•

Overlaid mode 1, set GPIO_ALT[1][n], GPIO_ALT[0][n]=1.

•

Overlaid mode 2, set GPIO_ALT[1][n], GPIO_ALT[0][n]=2.

Table 259 •

GPIO Registers

Description

DEVCPU_GCB::GPIO_OUT

Value to drive on GPIO outputs

DEVCPU_GCB::GPIO_OUT_SET

Atomic set of bits in GPIO_OUT

DEVCPU_GCB::GPIO_OUT_CLR

Atomic clear of bits in GPIO_OUT

DEVCPU_GCB::GPIO_IN

Current value on the GPIO pins

DEVCPU_GCB::GPIO_OE

Enable of GPIO output mode (drive GPIOs)

DEVCPU_GCB::GPIO_ALT

Enable of overlaid GPIO functions

DEVCPU_GCB::GPIO_INTR

Interrupt on changed GPIO value

DEVCPU_GCB::GPIO_INTR_ENA

Enable interrupt on changed GPIO value

DEVCPU_GCB::GPIO_INTR_IDENT

Currently interrupting sources

DEVCPU_GCB::GPIO_SD_MAP

Mapping of parallel signal detects

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