VSC7440 datasheet(366/444 Pages) MICROSEMI

366 / 444 page

VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

349

Setting CTRL.ENABLE enables the controller. The controller can be disabled by clearing the

CTRL.ENABLE field, there is a chance that disabling is not allowed (at the time when it is attempted); the

ENABLE_STATUS register shows if the controller was successful disabled.

Before enabling the controller, the user must decide on either standard or fast mode (CFG.SPEED) and

configure clock dividers for generating the correct timing (SS_SCL_HCNT, SS_SCL_LCNT,

FS_SCL_HCNT, FS_SCL_LCNT, and SDA_SETUP). The configuration of the divider registers depends

on the VCore-III system clock frequency. The register descriptions explain how to calculate the required

values.

Some two-wire serial devices require a hold time on TWI_SDA after TWI_SCL when transmitting from

the two-wire serial interface controller. The device supports a configurable hold delay through the

TWI_CONFIG register.

The two-wire serial interface controller has an 8-byte combined receive and transmit FIFO.

During normal operation of the two-wire serial interface controller, the STATUS register shows the activity

and FIFO states.

Figure 122 •

Two-Wire Serial Interface Timing for 7-bit Address Access

4.8.6.1

Two-Wire Serial Interface Addressing

To configure either 7-bit or 10 bit addressing, use CFG.MASTER_10BITADDR.

The two-wire serial interface controller can generate both General Call and START Byte. Initiate this

through TAR.GC_OR_START_ENA or TAR.GC_OR_START. The target/slave address is configured

using the TAR register.

4.8.6.2

Two-Wire Serial Interface Interrupt

The two-wire serial interface controller can generate a multitude of interrupts. All of these are described

in the RAW_INTR_STAT register. The RAW_INTR_STAT register contains interrupt fields that are always

set when their trigger conditions occur. The INTR_MASK register is used for masking interrupts and

allowing interrupts to propagate to the INTR_STAT register. When set in the INTR_STAT register, the

two-wire serial interface controller asserts interrupt toward the VCore-III interrupt controller.

The RAW_INTR_STAT register also specifies what is required to clear the specific interrupts. When the

source of the interrupt is removed, reading the appropriate CLR_* register (for example,

CLR_RX_OVER) clears the interrupt.

4.8.6.3

Built-in Two-Wire Serial Multiplexer

The device has built-in support for connecting to multiple two-wire serial devices that use the same two-

wire serial address. This is done by using the multiplexed clock outputs (TWI_SCL_Mn) for the two-wire

serial devices rather than TWI_SCL. Depending on which device or devices it needs to talk to, software

can then enable/disable the various clocks. This multiplexing feature is available for the first two-wire

serial interface controller instance.

From the two-wire serial controllers point of view, it does not know if it is using TWI_SCL or

TWI_SCL_Mn clocks. When using multiplexed mode, software needs to enable/disable individual

TWI_SCL_Mn connections before initiating the access operation using the two wire serial controller.

TWI2_SDA/GPIO

I/O

Two-wire serial interface 2 data, open-collector output.

Table 256 •

Two-Wire Serial Interface Pins (continued)

Pin Name

I/O

Description

Address / Command

TWI_SCL

TWI_SDA

R/W

ACK

917

Data

START

STOP

VSC7440 Datasheet(PDF) 366 Page - Microsemi Corporation

VSC7440 Datasheet(HTML) 366 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL