VSC7440 datasheet(368/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

351

Figure 123 •

MII Management Timing

4.8.7.1

Clock Configuration

The frequency of the management interface clock generated by the MIIM controller is derived from the

switch core’s frequency. The MIIM clock frequency is configurable and is selected with

MII_CFG.MIIM_CFG_PRESCALE. The calculation of the resulting frequency is explained in the register

description for MII_CFG.MIIM_CFG_PRESCALE. The maximum frequency of the MIIM clock is 25 MHz.

4.8.7.2

MII Management PHY Access

Reads and writes across the MII management interface are performed through the MII_CMD register.

Details of the operation, such as the PHY address, the register address of the PHY to be accessed, the

operation to perform on the register (for example, read or write), and write data (for write operations), are

set in the MII_CMD register. When the appropriate fields of MII_CMD are set, the operation is initiated by

writing 0x1 to MII_CMD.MIIM_CMD_VLD. The register is automatically cleared when the MIIM command

is initiated. When initiating single MIIM commands, MII_CMD.MIIM_CMD_SCAN must be set to 0x0.

When an operation is initiated, the current status of the operation can be read in MII_STATUS. The fields

MII_STATUS.MIIM_STAT_PENDING_RD and MII_STATUS.MIIM_STAT_PENDING_WR can be used to

poll for completion of the operation. For a read operation, the read data is available in

MII_DATA.MIIM_DATA_RDDATA after completion of the operation. The value of

MII_DATA.MIIM_DATA_RDDATA is only valid if MII_DATA.MIIM_DATA_SUCCESS indicates no read

errors.

The MIIM controller contains a small command FIFO. Additional MIIM commands can be queued as long

as MII_STATUS.MIIM_STAT_OPR_PEND is cleared. Care must be taken with read operations, because

multiple queued read operations will overwrite MII_DATA.MIIM_DATA_RDDATA.

Note: A typical software implementation will never queue read operations, because the software needs read

data before progressing the state of the software. In this case, MIIM_STATUS.MIIM_STAT_OPR_PEND

is checked before issuing MIIM read or write commands, for read operations

MII_STATUS.MIIM_STAT_BUSY is checked before returning read result.

By default, the MIIM controller operates in Clause 22 mode. To access Clause 45 compatible PHYs,

MII_CFG.MIIM_ST_CFG_FIELD and MII_CMD.MIIM_CMD_OPR_FIELD must be set according to

Clause 45 mode of operation.

4.8.7.3

PHY Scanning

The MIIM controller can be configured to continuously read certain PHY registers and detect if the read

value is different from an expected value. If a difference is detected, a special sticky bit register is set or

a CPU interrupt is generated, or both. For example, the controller can be programmed to read the status

registers of one or more PHYs and detect if the Link Status changed since the sticky register was last

read.

The reading of the PHYs is performed sequentially with the low and high PHY numbers specified in

MII_SCAN_0 as range bounds. The accessed address within each of the PHYs is specified in

MII_CMD.MIIM_CMD_REGAD. The scanning begins when a 0x1 is written to

MII_CMD.MIIM_CMD_SCAN and a read operation is specified in MII_CMD.MIIM_CMD_OPR_FIELD.

Setting MII_CMD.MIIM_CMD_SINGLE_SCAN stops the scanning after all PHYs have been scanned

one time. The remaining fields of MII_CMD register are not used when scanning is enabled.

The expected value for the PHY register is set in MII_SCAN_1.MIIM_SCAN_EXPECT. The expected

value is compared to the read value after applying the mask set in MII_SCAN_1.MIIM_SCAN_MASK. To

don’t-care a bit-position, write a 0 to the mask. If the expected value for a bit position differs from the read

MDC

MDIO

preamble

32 bit

2 bit

PHYAD

5 bit

REGAD

5 bit

2 bit

Address/data

16 bit

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