VSC7440 datasheet(367/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

350

Feedback on the clock (from slow two-wire serial devices) is automatically done for the TWI_SCL_Mn

lines that are enabled.

To enable multiplexed clocks, first configure the TWI_SCL_Mn overlaid mode in the GPIO controller.

Individual TWI_SCL_Mn clocks are then enabled by writing 1 to the corresponding GPIO output bit (in

DEVCPU_GCB::GPIO_OUT). To disable the clock, write 0 to the GPIO output bit. Disabled

TWI_SCL_Mn clocks are not driven during access and the feedback is disabled.

Note: In multiprocessor systems, the DEVCPU_GCB::GPIO_OUT_SET and

DEVCPU_GCB::GPIO_OUT_CLR registers can be used to avoid race conditions.

4.8.7

MII Management Controller

This section provides information about the MII Management (MIIM) controllers. The following table lists

the registers associated with the MII Management controllers.

The device contains two MIIM controllers with equal functionality. Data is transferred on the MIIM

interface using the Management Frame Format protocol specified in IEEE 802.3, Clause 22 or the MDIO

Manageable Device protocol defined in IEEE 802.3, Clause 45. The Clause 45 protocol differs from the

Clause 22 protocol by using indirect register access to increase the address range. The controller

supports both Clause 22 and Clause 45. The first MIIM controller is connected to the internal PHYs of the

device.

The MIIM interface pins for the second controller are overlaid functions on the GPIO interface. Before

using this MIIM controller, the overlaid functions for the appropriate GPIO pins must first be enabled. For

more information about overlaid functions on the GPIOs for these signals, see GPIO Overlaid Functions,

page 352.

The MDIO signal is changed or sampled on the falling edge of the MDC clock by the controller. The

MDIO pin is tri-stated in-between access and when expecting read data.

Table 257 •

MIIM Registers

Description

DEVCPU_GCB::MII_STATUS

Controller status

DEVCPU_GCB::MII_CMD

Command and write data

DEVCPU_GCB::MII_DATA

Read data

DEVCPU_GCB::MII_CFG

Clock frequency configuration

DEVCPU_GCB::MII_SCAN_0

Auto-scan address range

DEVCPU_GCB::MII_SCAN_1

Auto-scan mask and expects

DEVCPU_GCB::MII_SCAN_LAST_RSLTS

Auto-scan result

DEVCPU_GCB::MII_SCAN_LAST_RSLTS_VLD

Auto-scan result valid

DEVCPU_GCB:: MII_SCAN_RSLTS_STICKY

Differences in expected versus read auto-scan

Table 258 •

MIIM Management Controller Pins

Pin Name

I/O

Description

MDC1/GPIO

MIIM clock for controller 1

MDIO1/GPIO

I/O

MIIM data input/output for controller 1

VSC7440 Datasheet(PDF) 367 Page - Microsemi Corporation

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