VSC7440 datasheet(363/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

346

By setting TIMER_CTRL[n].ONE_SHOT_ENA, the timer disables itself after generating one interrupt. By

default, timers will decrement, interrupt, and reload indefinitely (or until disabled by clearing

TIMER_CTRL[n].TIMER_ENA).

A timer can be reloaded from TIMER_RELOAD_VALUE[n] at the same time as it is enabled by setting

TIMER_CTRL[n].FORCE_RELOAD and TIMER_CTRL[n].TIMER_ENA at the same time.

Example Configure Timer0 to interrupt every 1 ms. With the default timer tick of 100 µs ten timer ticks

are needed for a timer that wraps every 1 ms. Configure TIMER_RELOAD_VALUE[0] to 0x9, then

enable the timer and force a reload by setting TIMER_CTRL[0].TIMER_ENA and

TIMER_CTRL[0].FORCE_RELOAD at the same time.

4.8.5

UARTs

This section provides information about the UART (Universal Asynchronous Receiver/Transmitter)

controllers. There are two independent UART controller instances in the VCore-III system: UART and

UART2. These instances are identical copies and anywhere in this description the word UART can be

replaced by UART2.

The following table lists the registers associated with the UART.

The VCore-III system UART is functionally based on the industry-standard 16550 UART (RS232

protocol). This implementation features a 16-byte receive and a 16-byte transmit FIFO.

Figure 121 •

UART Timing

The number of data bits, parity, parity-polarity, and stop-bit lengths are all programmable using LCR.

The UART pins on the device are overlaid functions on the GPIO interface. Before enabling the UART,

the VCore-III CPU must enable overlaid modes for the appropriate GPIO pins. For more information

about overlaid functions on the GPIOs for these signals, see GPIO Overlaid Functions, page 352.

The following table lists the pins of the UART interfaces.

Table 253 •

UART Registers

Description

UART::RBR_THR

Receive buffer/transmit buffer/Divisor (low)

UART::IER

Interrupt enable/divisor (high)

UART::IIR_FCR

Interrupt identification/FIFO control

UART::LCR

Line control

UART::MCR

Modem control

UART::LSR

Line status

UART::MSR

Modem status

UART::SCR

Scratchpad

UART::USR

UART status

Table 254 •

UART Interface Pins

Pin Name

I/O

Description

UART_RXD/GPIO

UART receive data

1, 1.5, or 2 stop bit(s)

1 start bit

5 to 8 data bits (LSB first) +

optional parity

One Character

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