VSC7440 datasheet(361/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

344

The memory controller automatically clears MEMCTRL_CTRL.INITIALIZE and sets the

MEMCTRL_STAT.INIT_DONE field after the controller and the memory module (or modules) are

operational. Software must wait for the INIT_DONE indication before continuing to calibrate the read

window.

4.8.3.5

DQS Read Window Calibration

After initialization of the memory controller, successful writes to the memory are guaranteed. Reading is

not yet possible, because the round trip delay between controller and memory modules are not

calibrated.

Calibration of the read window includes writing a known value to the start of the DDR memory and then

continually reading this value while adjusting the DQS window until the correct value is read from the

memory. The calibration procedure depends on the number of byte lanes that are used (see

MEMCTRL_CFG.DDR_WIDTH).

Note: For an ECC system, the calibration procedure for two byte lanes must be used, because the memory

controller is initialized without ECC enabled.

Calibration of One Byte Lane

The following procedure applies to systems where MEMCTRL_CFG.DDR_WIDTH is 0:

•

Write 0x000000FF to SBA address 0x20000000.

•

Set the MEMCTRL_DQS_DLY[0].DQS_DLY field to 0.

Perform the following steps to calibrate the read window. Do not increment the DQS_DLY field beyond its

maximum value. If the DQS_DLY maximum value is exceeded, it is an indication something is incorrect,

and the memory controller will not be operational.

Read byte address 0x20000000. If the content is different from 0xFF, increment

MEMCTRL_DQS_DLY[0].DQS_DLY by one, and repeat step 1, else continue to step 2.

Read byte address 0x20000000. If the content is different from 0x00, increment

MEMCTRL_DQS_DLY[0].DQS_DLY by one, and repeat step 2, else continue to step 3.

Decrement MEMCTRL_DQS_DLY[0].DQS_DLY by three.

After the last step, which configures the appropriate DQS read window, the memory is ready for random

read and write operations. For more information about ECC or 1 gigabyte support, see ECC and 1-

Gigabyte Support, page 345.

Calibration of Two Byte Lanes

This procedure applies to systems where MEMCTRL_CFG.DDR_WIDTH is 1:

•

Write 0x0000FFFF to SBA address 0x20000000.

•

Write 0x00000000 to SBA address 0x20000004.

•

Set the MEMCTRL_DQS_DLY[0].DQS_DLY field to 0.

•

Set the MEMCTRL_DQS_DLY[1].DQS_DLY field to 0.

Perform the following steps to calibrate the read window. Do not increment the DQS_DLY fields beyond

their maximum value. If a DQS_DLY maximum value is exceeded, it is an indication something is

incorrect, and the memory controller will not be operational.

Read byte addresses 0x20000000 and 0x20000001 from memory.

If the contents of byte address 0x20000000 is different from 0xFF, increment

MEMCTRL_DQS_DLY[0].DQS_DLY by one.

If the contents of byte address 0x20000001 is different from 0xFF, increment

MEMCTRL_DQS_DLY[1].DQS_DLY by one.

If any DQS_DLY was incremented repeat step 1, else continue to step 2.

Read byte addresses 0x20000000 and 0x20000001 from memory.

If the contents of byte address 0x20000000 is different from 0x00, increment

MEMCTRL_DQS_DLY[0].DQS_DLY by one.

If the contents of byte address 0x20000001 is different from 0x00, increment

VSC7440 Datasheet(PDF) 361 Page - Microsemi Corporation

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