VSC7440 datasheet(362/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

345

MEMCTRL_DQS_DLY[1].DQS_DLY by one.

If any DQS_DLY was incremented repeat step 2, else continue to step 3.

Decrement MEMCTRL_DQS_DLY[0].DQS_DLY by three, and decrement MEMCTRL_DQS_DLY[1]

by three.

The last step configures the appropriate DQS read windows. After this step the memory is ready for

random read and write operations. If ECC or 1 gigabyte is needed, see ECC and 1 Gigabyte Support.

4.8.3.6

ECC and 1-Gigabyte Support

The memory controller supports ECC, allowing correction of single bit and detection of two bit errors in

every byte that is read from memory.

When ECC is enabled, one byte lane is used for data words and the other is used for ECC check-word.

After enabling ECC, the amount of memory available to software is half of the physical memory (the

lower half of the memory region).

ECC support must be enabled just after read calibration by setting MEMCTRL_CFG.DDR_ECC_ENA = 1

and at the same time setting MEMCTRL_CFG.BURST_SIZE = 0.

When ECC is enabled, the memory controller automatically corrects single-bit errors and detects two-bit

errors. It is possible to propagate these events to the SBA to trigger a bus-error event in the VCore-III

CPU. Non-correctable error indications are forwarded when

MEMCTRL_CFG.DDR_ECC_ERR_ENA = 1. Correctable “errors” are forwarded when

MEMCTRL_CFG.DDR_ECC_COR_ENA = 1. The VCore-III CPU can generate interrupt on these events

so that software can take the appropriate action.

The memory controller supports up to 1 gigabyte of physical memory. To access more than 512

megabytes from the VCore-III CPU, set MEMCTRL_CFG.DDR_512MBYTE_PLUS = 1 to change the

SBA memory map. For more information, see Shared Bus. When ECC is enabled with 1 gigabyte of

physical memory, MEMCTRL_CFG.DDR_512MBYTE_PLUS does not have to be set, because only half

of the physical memory is available to software.

4.8.4

Timers

This section provides information about the timers. The following table lists the registers associated with

timers.

There are three decrementing 32-bit timers in the VCore-III system that run from a common divider. The

common divider is driven by a fixed 250 MHz clock and can generate timer ticks from 0.1 µs (10 MHz) to

1 ms (1 kHz), configurable through TIMER_TICK_DIV. The default timer tick is 100 µs (10 kHz).

Software can access each timer value through the TIMER_VALUE[n] registers. These can be read or

written at any time, even when the timers are active.

When a timer is enabled through TIMER_CTRL[n].TIMER_ENA, it decrements from the current value

until it reaches zero. An attempt to decrement a TIMER_VALUE[n] of zero generates interrupt and

assigns TIMER_VALUE[n] to the contents of TIMER_RELOAD_VALUE[n]. Interrupts generated by the

timers are sent to the VCore-III interrupt controller. From here, interrupts can be forwarded to the

VCore-III CPU or to an external CPU. For more information, see Interrupt Controller.

Table 252 •

Timer Registers

Description

ICPU_CFG::TIMER_CTRL

Enable/disable timer

ICPU_CFG::TIMER_VALUE

Current timer value

ICPU_CFG::TIMER_RELOAD_VALUE Value to load when wrapping

ICPU_CFG::TIMER_TICK_DIV

Common timer-tick divider

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