VSC7440 datasheet(364/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

347

The baud rate of the UART is derived from the VCore-III system frequency. The divider value is indirectly

set through the RBR_THR and IER registers. The baud rate is equal to the VCore-III system clock

frequency, divided by 16, and multiplied by the value of the baud rate divisor. A divider of zero disables

the baud rate generator and no serial communications occur. The default value for the divisor register is

zero.

Example Configuring a baud rate of 9600 in a 250 MHz VCore-III system. To generate a baud rate of

9600, the divisor register must be set to 0x65C (250 MHz/(16 × 9600 Hz)). Set LCR.DLAB and write

0x5C to RBR_THR and 0x06 to IER (this assumes that the UART is not in use). Finally, clear LCR.DLAB

to change the RBR_THR and IER registers back to the normal mode.

By default, the FIFO mode of the UART is disabled. Enabling the 16-byte receive and 16-byte transmit

FIFOs (through IIR_FCR) is recommended.

Note: Although the UART itself supports RTS and CTS, these signals are not available on the pins of the

device.

4.8.5.1

UART Interrupt

The UART can generate interrupt whenever any of the following prioritized events are enabled (through

IER).

•

Receiver error

•

Receiver data available

•

Character timeout (in FIFO mode only)

•

Transmit FIFO empty or at or below threshold (in programmable THRE interrupt mode)

When an interrupt occurs, the IIR_FCR register can be accessed to determine the source of the interrupt.

Note that the IIR_FCR register has different purposes when reading or writing. When reading, the

interrupt status is available in bits 0 through 3. For more information about interrupts and how to handle

them, see the IIR_FCR register description.

Example Enabling interrupt when transmit fifo is below one-quarter full. To get this type of interrupt, the

THRE interrupt must be used. First, configure TX FIFO interrupt level to one-quarter full by setting

IIR_FCR.TET to 10; at the same time, ensure that the IIR_FCR.FIFOE field is also set. Set IER.PTIME to

enable the THRE interrupt in the UART. In addition, the VCore-III interrupt controller must be configured

for the CPU to be interrupted. For more information, see Interrupt Controller.

4.8.6

Two-Wire Serial Interface

This section provides information about the two-wire serial interface controllers. There are two

independent two-wire serial interface controller instances in the VCore-III system, TWI and TWI2. These

instances are identical copies and anywhere in this description the word TWI can be replaced by TWI2.

The following table lists the registers associated with the two-wire serial interface.

UART_TXD/GPIO

UART transmit data

UART2_RXD/GPIO

UART2 receive data

UART2_TXD/GPIO

UART2 transmit data

Table 255 •

Two-Wire Serial Interface Registers

Description

TWI::CFG

General configuration.

TWI::TAR

Target address.

TWI::SAR

Slave address.

TWI::DATA_CMD

Receive/transmit buffer and command.

Table 254 •

UART Interface Pins (continued)

Pin Name

I/O

Description

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