VSC7440 datasheet(360/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

343

The memory controller supports two chip selects and automatically selects modules based on the

configured address width and bank count. The resulting pool of memory is one large consecutive region.

4.8.3.2

On-Die Termination

An end termination scheme must be configured when writing from the device to the memory modules,

the memory module furthest away from the device must be connected to the ODT output. Enable

assertion of ODT output for all write access by setting MEMCTRL_TERMRES_CTRL = 0x0000000C.

Figure 120 •

Memory Controller ODT Hookup

4.8.3.3

Enabling and Calibrating SSTL I/Os

Prior to controller initialization, the device’s SSTL I/O drivers must be enabled and calibrated to correct

drive strength and termination resistor values. It is recommended that the device’s I/O drive and

termination strengths be 60

Ω/60 Ω.

Complete the following tasks to enable and calibrate the SSTL I/Os.

Enable the SSTL mode by clearing MEMPHY_CFG.PHY_RST and setting

MEMPHY_CFG.PHY_SSTL_ENA.

Perform calibration with the previously mentioned drive and termination strengths by writing 0xEF to

MEMPHY_ZCAL.

Wait until MEMPHY_ZCAL.ZCAL_ENA is cleared (indicates calibration is done).

Enable drive of the SSTL I/Os by setting MEMPHY_CFG.PHY_CK_OE,

MEMPHY_CFG.PHY_CL_OE, and MEMPHY_CFG.PHY_ODT_OE.

The SSTL interface is now enabled and calibrated, and the initialization of the memory controller can

commence.

4.8.3.4

Memory Controller and Module Initialization

After memory controller parameters are configured, and after the SSTL I/Os are enabled and calibrated,

the memory controller and modules are initialized by setting MEMCTRL_CTRL.INITIALIZE.

During initialization, the memory controller automatically follows the proper JEDEC defined procedure for

initialization and writing of mode registers to the DDR3/DDR3L memory modules.

MEMCTRL_MR1_VAL.MR1_VAL

Set to MR1.

MEMCTRL_MR2_VAL.MR2_VAL

Set to MR2.

MEMCTRL_MR3_VAL.MR3_VAL

Set to MR3.

Table 251 •

Memory Controller Configuration (continued)

Description

DDR2/3

Memory

Controller

Memory Module

Byte Lane 1

CS0

CS1

Byte Lane 0

ODT

CS#

Memory Module

CS#

ODT

Memory Module

CS#

ODT

Memory Module

CS#

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