VSC7440 datasheet(358/444 Pages) MICROSEMI

358 / 444 page

VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

341

The following steps are required to bring up the memory controller.

Release the controller from reset by clearing RESET.MEM_RST_FORCE.

Configure timing and mode parameters. These depend on the DDR3/DDR3L module and

configuration selected for the device. For more information, see DDR3/DDR3L Timing and Mode

Configuration Parameters, page 341.

Enable and calibrate the SSTL I/Os. For more information, see Enabling and Calibrating SSTL I/Os.

Initialize the memory controller and modules. For more information, see Memory Controller and

Module Initialization.

Calibrate the DQS read window. For more information, see DQS Read Window Calibration.

Optionally configure ECC and 1 gigabyte support. For more information, see ECC and 1-Gigabyte

Support, page 345.

4.8.3.1

DDR3/DDR3L Timing and Mode Configuration Parameters

This section provides information about each of the parameters that must be configured prior to

initialization of the memory controller. It provides a quick overview of fields that must be configured and

their recommended values. For more information about each field, see the register list.

The memory controller operates at 312.5 MHz, and the corresponding DDR clock period is 3.2 ns

(DDR625). When a specific timing value is used in this section (for example, tMOD), it means that the

corresponding value from the memory module datasheet is expressed in memory controller clock cycles

(divided by 3.2 ns and rounded up and possibly adjusted for minimum clock cycle count).

The following table defines general parameters for DDR3/DDR3L required when configuring the memory

controller.

The following table lists the memory controller registers that must be configured before initialization. It is

recommended to configure all fields listed, even when ODT or dual row configurations are not used.

Table 250 •

General DDR3/DDR3L Timing and Mode Parameters

Parameter

DDR3/DDR3L

CWL

tMOD

tXPR

tDLLK

tRP

FAW

tFAW

MR0

((RL-4)<<4) | ((tWR-4)<<9)

MR1

0x0040

MR2

((WL-5)<<3)

MR3

0x0000

Table 251 •

Memory Controller Configuration

Description

MEMCTRL_CFG.DDR_MODE

Set to 1 for DDR3/DDR3L mode.

VSC7440 Datasheet(PDF) 358 Page - Microsemi Corporation

VSC7440 Datasheet(HTML) 358 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL