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VSC7440 Datasheet(PDF) 354 Page - Microsemi Corporation

Part # VSC7440
Description  L2/L3 Enterprise Gigabit Ethernet Switch with 10 Gbps Links
PDF  444 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VSC7440 Datasheet(HTML) 354 Page - Microsemi Corporation

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VCore-III System and CPU Interfaces
VMDS-10492 VSC7440 Datasheet Revision 4.2
337
For SPI mode, chip select is asserted throughout transfers. Transmit transfers end when the transmit
FIFO runs out of data frames. Software must make sure it is not interrupted while writing data for a
multiframe transfer. When multiple distinct transfers are needed, wait for SR.TFE = 1 and SR.BUSY = 0
before initiating new transfer. SR.BUSY is an indication of ongoing transfers, however, it is not asserted
immediately when writing frames to the FIFO. As a result, software must also check the SR.TFE
(transmit FIFO empty) indication.
The SI master controller supports up to 16 chip selects. Chip select 0 is mapped to the SI_nCS pin of the
serial interface. The remaining chips selects are available using overlaid GPIO functions. Software
controls which chip selects to activate for a transfer using the SER register. For more information about
overlaid functions on the GPIOs for these signals, see GPIO Overlaid Functions, page 352.
Writing to any DR replication index put data into the transmission FIFO, and reading from any DR
replication index take out data from the receive FIFO. FIFO status indications are available in the SR
register’s TFE, TFNF, RFF, and RFNE fields. For information about interrupting on FIFO status, see
SIMC Interrupts, page 339.
After completing all initial configurations, the SI master controller is enabled by writing
SIMCEN.SIMCEN = 1. Some registers can only be written when the controller is in disabled state. This is
noted in the register-descriptions for the affected registers.
4.8.2.1
SPI Protocol
When the SI master controller is configured for SPI mode, clock polarity and position is configurable in
CTRLR0.SCPH and CTRLR0.SCPOL. The following illustration shows the four possible combinations for
8-bit transfers.
Table 248 •
SI Master Controller Pins
Pin Name
I/O
Description
SI_nCS0
SI_nCS[15:1]/GPIO
O
Active low chip selects. Chip selects 1 through
15 are overlaid functions on the GPIO pins.
SI_CLK
O
Clock output.
SI_DO
O
Data output (MOSI).
SI_DI
I
Data input (MISO).



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