VSC7440 datasheet(352/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

335

the VCore-III CPU. This greatly optimizes reading from sequential addresses in the Flash, such as when

copying data from Flash into program memory.

The following illustrations depict 24-bit address mode. When the controller is set to 32-bit mode (through

SPI_MST_CFG.A32B_ENA), 32 address bits are transferred instead of 24.

Figure 116 •

SI Read Timing in Normal Mode

Figure 117 •

SI Read Timing in Fast Mode

The default timing of the SI boot controller operates with most serial interface Flash devices. Use the

following process to calculate the optimized serial interface parameters for a specific SI device:

Calculate an appropriate frequency divider value as described in SPI_MST_CFG.CLK_DIV. The SI

operates at no more than 25 MHz, and the maximum frequency of the SPI device must not be

exceeded. The VCore-III system frequency in the device is 250 MHz.

The SPI device may require a FAST_READ command rather than normal READ when the SI

frequency is increased. Setting SPI_MST_CFG.FAST_READ_ENA makes the SI boot controller use

FAST_READ commands.

Calculate SPI_MST_CFG.CS_DESELECT_TIME so that it matches how long the SPI device

requires chip-select to be deasserted between access. This value depends on the SI clock period

that results from the SPI_MST_CFG.CLK_DIV setting.

These parameters must be written to SPI_MST_CFG. The CLK_DIV field must either be written last or at

the same time as the other parameters. The SPI_MST_CFG register can be configured while also

booting up from the SI.

When the VCore-III CPU boots from the SI interface, the default values of the SPI_MST_CFG register

are used until the SI_MST_CFG is reconfigured with optimized parameters. This implies that SI_CLK is

operating at approximately 8.1 MHz, with normal read instructions and maximum gap between chip

select operations to the Flash.

Note: The SPI boot master does optimized reading. SI_DI (from the Flash) is sampled just before driving falling

edge on SI_CLK (to the Flash). This greatly relaxes the round trip delay requirement for SI_CLK to SI_DI,

allowing high Flash clock frequencies.

4.8.2

SI Master Controller

This section describes the SPI master controller (SIMC) and how to use it for accessing external SPI

slave devices, such as programming of a serially attached Flash device on the boot interface. VCore

booting from serial Flash is handled by the SI boot master.

SI_nCS0

SI_CLK

SI_DO

SI_DI

9876 5 4 3210

READ

543 2 1 0

Data Byte #0

24 Bit Address

54 32 1 0

Data Byte #1

5432 1 0

Data Byte #2

54 3210

Data Byte #3

SI_nCS0

SI_CLK

SI_DO

SI_DI

0 9 8 7 6 543 21 0

FAST_READ

5 432 10

Data Byte #0

24 Bit Address

54 32 1 0

Data Byte #1

543 21 0

Data Byte #2

543 21 0

Data Byte #3

Dummy Byte

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