VSC7440 datasheet(351/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

334

By default, the SI boot controller operates in 24-bit address mode. In this mode, there are four

programmable chip selects when the VCore-III system controls the SI. Each chip select can address up

to 16 megabytes (MB) of memory.

Figure 114 •

SI Boot Controller Memory Map in 24-Bit Mode

The SI boot controller can be reconfigured for 32-bit address mode through SPI_MST_CFG.A32B_ENA.

In 32-bit mode, the entire SI region of 256 megabytes (MB) is addressed using chip select 0.

Figure 115 •

SI Boot Controller Memory Map in 32-Bit Mode

Reading from the memory region for a specific SI chip select generates an SI read on that chip select.

The VCore-III CPU can execute code directly from Flash by executing from the SI boot controller’s

memory region. For 32-bit capable SI Flash devices, the VCore-III must start up in 24-bit mode. During

the boot process, it must manually reconfigure the Flash device (and SI boot controller) into 32-bit mode

and then continue booting.

The SI boot controller accepts 8-bit, 16-bit, and 32-bit read access with or without bursting. Writing to the

SI requires manual control of the SI pins using software. Setting SW_MODE.SW_PIN_CTRL_MODE

places all SI pins under software control. Output enable and the value of SI_CLK, SI_DO, SI_nCSn are

controlled through the SW_MODE register. The value of the SI_DI pin is available in

SW_MODE.SW_SPI_SDI. The software control mode is provided for legacy reasons; new

implementations should use the dedicated master controller for writing to the serial interface. For more

information see SI Master Controller, page 335.

Note: The VCore-III CPU cannot execute code directly from the SI boot controller’s memory region at the same

time as manually writing to the serial interface.

The following table lists the serial interface pins when the SI boot controller is configured as owner of SI

interface in GENERAL_CTRL.IF_SI_OWNER. For more information about overlaid functions on the

GPIOs for these signals, see GPIO Overlaid Functions, page 352.

The SI boot controller does speculative prefetching of data. After reading address n, the SI boot

controller automatically continues reading address n + 1, so that the next value is ready if requested by

Table 246 •

Serial Interface Pins

Pin Name

I/O

Description

SI_nCS0

SI_nCS[3:1]/GPIO

Active low chip selects. Only one chip select can be active at any

time. Chip selects 1 through 3 are overlaid functions on GPIO pins.

SI_CLK

Clock output.

SI_DO

Data output (MOSI).

SI_DI

Data input (MISO).

SI Controller Memory Map

Chip Select 0, SI_nCS0

SI Controller

16 MB

Chip Select 1, SI_nCS1

+0x01000000

16 MB

Chip Select 2, SI_nCS2

16 MB

Chip Select 3, SI_nCS3

16 MB

+0x02000000

+0x03000000

SI Controller Memory Map (32- bit)

Chip Select 0, SI_nCS0

SI Controller

256 MB

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