VSC7440 datasheet(353/444 Pages) MICROSEMI

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VCore-III System and CPU Interfaces

VMDS-10492 VSC7440 Datasheet Revision 4.2

336

The following table lists the registers associated with the SI master controller.

The SI master controller supports Motorola SPI and Texas Instruments SSP protocols. The default

protocol is SPI, enable SSP by setting CTRLR0.FRF = 1 and GENERAL_CTRL.SSP_MODE_ENA = 1.

The protocol baud rate is programmable in BAUDR.SCKDV; the maximum baud rate is 25 MHz.

Before the SI master controller can be used, it must be set as owner of the serial interface. This is done

by writing GENERAL_CTRL.IF_SI_OWNER = 2.

The SI master controller has a programmable frame size. The frame size is the smallest unit when

transferring data over the SI interface. Using CTRLR0.DFS, the frame size is configured in the range of 4

bits to 16 bits. When reading or writing words from the transmit/receive FIFO, the number of bits that is

stored per FIFO-word is always equal to frame size (as programmed in CTRLR0.DFS).

The controller operates in one of three following major modes: Transmit and receive, transmit only, or

receive only. The mode is configured in CTRLR0.TMOD.

Transmit and receive. software paces SI transactions. For every data frame that software writes to the

transmission FIFO, another data frame is made available in the receive FIFO (receive data from the

serial interface). Transaction will go on for as long as there is data available in the transmission FIFO.

Transmit only. Software paces SI transactions. The controller transmits only; receive data is discarded.

Transaction will go on for as long as there is data available in the transmission FIFO.

Receive only. The controller paces SI transactions. The controller receives only data, software requests

a specific number of data frames by means of CTRLR1.NDF, the transaction will go on until all data

frames has been read from the SI interface. Transaction is initiated by software writing one data frame to

transmission FIFO. This frame is not used for anything else than starting the transaction. The SI_DO

output is undefined during receive only transfers. Receive data frames are put into the receive FIFO as

they are read from SI.

Table 247 •

SI Master Controller Configuration Registers Overview

Description

SIMC::CTRLR0

Transaction configuration

SIMC::CTRLR1

Configurations for receive-only mode

SIMC::SIMCEN

SI master controller enable

SIMC::SER

Slave select configuration

SIMC::BAUDR

Baud rate configuration

SIMC::TXFTLR

Tx FIFO threshold level

SIMC::RXFTLR

Rx FIFO Threshold Level

SIMC::TXFLR

Tx FIFO fill level

SIMC::RXFLR

Rx FIFO fill level

SIMC::SR

Various status indications

SIMC::IMR

Interrupt enable

SIMC::ISR

Interrupt sources

SIMC::RISR

Unmasked interrupt sources

SIMC::TXOICR

Clear of transmit FIFO overflow interrupt

SIMC::RXOICR

Clear of receive FIFO overflow interrupt

SIMC::RXUICR

Clear of receive FIFO underflow interrupt

SIMC::DR

Tx/Rx FIFO access

ICPU_CFG::GENERAL_CTRL

Interface configurations

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